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Commit Graph
2794 Commits
Author SHA1 Message Date
Lioncache 5e88be3c99 ARMEmitter: Handle SVE MUL immediate (unpredicated) 2023-07-28 19:55:06 -04:00
Lioncache be52844ce0 ARMEmitter: Handle SVE MIN/MAX immediate (unpredicated) 2023-07-28 19:47:32 -04:00
Lioncache d629884147 ARMEmitter: Handle SVE ADD/SUB immediate (unpredicated) 2023-07-28 19:23:06 -04:00
Ryan Houdek 64c72430bf Merge pull request #2837 from lioncash/predicate 
Arm64/Emitter: Add remaining missing SVE predicate range assertions
 2023-07-28 14:44:43 -07:00
Lioncache 1b13e8db7d Arm64/Emitter: Simplify SVE constructive prefix 
Moves the assert and op definition into the implementing function.
Also enforces valid use of predicate registers.
 2023-07-28 17:17:51 -04:00
Lioncache 8557656259 Arm64/Emitter: Simplify SVE FP unary operations predicated group 
Moves the asserts into the implementation function and also enforces
valid use of predicates.
 2023-07-28 17:07:15 -04:00
Ryan Houdek c87c04db59 ARMEmitter: Implement cmn alias 
Inspired by #2832, since it was using adds directly.
cmn is an alias of adds with the destination register being zr.
 2023-07-28 13:58:23 -07:00
Ryan Houdek f5262446a0 Merge pull request #2833 from Sonicadvance1/remove_erroneous_asserts 
FEXCore: Remove erroneous asserts in the project
 2023-07-28 13:53:42 -07:00
Ryan Houdek a255813e99 FEXCore: Remove erroneous asserts in the project 
Inspired by #2832 by going through the source and removing uses of
`assert`.

assert doesn't work for us in debug builds because some games will
capture SIGABRT and continue running. So we need to use FEX's built in
assert handlers which call `FEX_TRAP_EXECUTION` which will take down the
FEX process as expected.

There wasn't too much usage of this in the source, so this is relatively
straightforward.
 2023-07-28 13:36:05 -07:00
Lioncache 4c6336b560 Arm64/Emitter: Simplify load/store contiguous (scalar plus scalar) group 
Lets us move the base opcode into the implementing function.
While we're at it, we can also add an assert to enforce predicate ranges.
 2023-07-28 16:30:34 -04:00
Lioncache 145c7799a5 Arm64/Emitter: Simplify load/store contiguous (scalar plus immediate) group 
We can move asserts and the base opcode into the implementing function.
While we're at it, we can add an assert to ensure predicate registers are in range.
 2023-07-28 16:30:34 -04:00
Lioncache 91df503e55 Arm64/Emitter: Simplify load/store multiple contiguous (scalar plus immediate) group 
We can centralize the base opcode and some of the asserts in the implementing function.
We can also add an assert that validates the predicate register range
and also make the offset assertions much more informative.
 2023-07-28 16:30:30 -04:00
Lioncache 3c417cee84 Arm64/Emitter: Reduce qualifying in SVE FP/Int Convert To FP/Int groups 
Since everything we need is already in the ARMEmitter namespace, we
don't need to qualify all type usages, which reduces the verbosity
a little during reading.
 2023-07-28 14:57:43 -04:00
Lioncache 857780b46e Arm64/Emitter: Fix sorting of SVE integer to float group 
This is actually already implemented but was grouped with the
SVE floating-point convert to integer group. We can extract this
out to be organized a little nicer.
 2023-07-28 14:52:57 -04:00
Lioncache cb34aa3dee Arm64/Emitter: Simplify SVE FP/Int Convert To FP/Int groups 
We can move the base opcode and asserts into the implementing function.
We can also add an assert to ensure the predicate is in a valid range.
 2023-07-28 14:44:54 -04:00
Lioncache 0d74777954 Arm64/Emitter: Simplify SVE FP Unary Operations Predicated group 
We can move the op into the implementing function and get rid of
an unnecessary function.

We can also add an assert to ensure the predicates are valid as well.
 2023-07-28 14:24:28 -04:00
Lioncache cc359f09ad Arm64/Emitter: Simplify SVE FP convert precision odd elements 
We can move the base opcode into the implementation function.
We can also add an assert to ensure that the predicate is in a valid range.
 2023-07-28 13:34:04 -04:00
Lioncache dedeba0575 Arm64/Emitter: Simplify SVE2 Character Match group 
We can move the base opcode into the implementation function.
 2023-07-28 13:34:04 -04:00
Lioncache dc3ccbcc43 Arm64/Emitter: Simplify SVE SEL instruction 
We can move the base opcode and asserts into the implementing function.
We can also implement the mov alias in terms of sel()
 2023-07-28 13:34:04 -04:00
Lioncache ebd9b49dbe Arm64/Emitter: Simplify SVE2 bitwise ternary operations category 
We can move the asserts into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache 43e21ad749 Arm64/Emitter: Simplify SVE permute vector elements category 
We can move the asserts and the base opcode into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache 1b3beec085 Arm64/Emitter: Add missing SVE TBL encoding 
Adds the missing SVE2 double table encoding.

Crosses off a TODO.
 2023-07-28 13:34:04 -04:00
Lioncache c88f2e0730 Arm64/Emitter: Simplify SVE table lookup category 
We can move the base opcode into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache 1645f6e582 Arm64/Emitter: Simplify SVE integer add/sub vectors unpredicated category 
We can move the base op encoding into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache e2baa1106b Context: Make alias for code invalidation functor 
Makes it so any changes wouldn't need to go across everything implementing the Context class.
 2023-07-27 18:59:15 -04:00
Lioncache 68880fd66b Context: Make alias for custom IR handlers 
Puts the type declaration in one place.
 2023-07-27 18:43:19 -04:00
Lioncache 8fc903cc51 Frontend: Remove unused ModRMDecoded instance 
This is assigned to but never used.
 2023-07-27 17:18:16 -04:00
Ryan Houdek c81b1c3432 Merge pull request #2825 from lioncash/lookup 
Frontend: Remove redundant lookups in BranchTargetInMultiblockRange()
 2023-07-27 14:00:40 -07:00
Lioncache db9ba16a53 Frontend: Remove redundant lookups in BranchTargetInMultiblockRange() 
insert() will only ever perform an insertion if the relevant element
doesn't exist within the set, so we were doing an unnecessary lookup
in two spots.

We don't use emplace() here because it will need to construct the
key for the element inside the allocated node (since the key may
be non-copyable/non-movable), causing an allocation even if an insert
doesn't actually occur.

Conversely, insert() will not need to allocate and construct a node
ahead of time if an element already exists in the set.
 2023-07-27 16:28:37 -04:00
Lioncache 6e140e9ff2 Arm64/Emitter: Simplify SVE Integer Compare With Unsigned Immediate category 
We can move the asserts into the implementation function.
 2023-07-27 14:12:16 -04:00
Lioncache d793f7295a Arm64/Emitter: Add missing cmpne signed immediate op 
Noticed while simplifying the signed immediate implementation.
 2023-07-27 14:08:26 -04:00
Lioncache 8f6018a1b4 Arm64/Emitter: Simplify SVE Integer Compare With Signed Immediate category 
We can move all asserts and handling into the implementation function.
 2023-07-27 14:03:34 -04:00
Lioncache 0a97d4456d Arm64/Emitter: Simplify SVE Predicate Logical Operations category 
We can move the base opcode into the implementation function.
 2023-07-27 13:51:48 -04:00
Lioncache c2dbe8309b Arm64/Emitter: Simplify SVE Bitwise Logical Operations Predicated category 
We can move the asserts and base opcode into the implementation function.
We can also add an assert to ensure a valid predicate range.
 2023-07-27 13:41:49 -04:00
Lioncache 06d66a0188 Arm64/Emitter: Simplify SVE Integer Mul/Div Vectors Predicated category 
We can move the base opcode into the implementation function.
We can also move the division assert into it as well.
 2023-07-27 13:36:22 -04:00
Lioncache ef254da7ca Arm64/Emitter: Simplify SVE Integer Min/Max/Difference Predicated category 
We can move the asserts into the implementation function and also add
another assert to validate the predicate range.
 2023-07-27 13:29:15 -04:00
Lioncache 162dcf3cd0 Arm64/Emitter: Simplify SVE Integer Add/Sub Vectors Predicated category 
We can move the opcode into the implementation function.
 2023-07-27 13:19:56 -04:00
Lioncache dcc47074d1 Arm64/Emitter: Simplify SVE Integer Multiply-Add Predicated category 
We can move the op definition into the implementation function.
 2023-07-27 13:16:11 -04:00
Lioncache 4dfee31012 Arm64/Emitter: Simplify SVE FP Recursive Reduction category 
We can move the op constant into the implementation function.
 2023-07-27 13:10:12 -04:00
Lioncache 3749fa6569 Arm64/Emitter: Simplify SVE Float Arithmetic Unpredicated category 
We can move the common assert and op value into the implementation function.
 2023-07-27 13:07:46 -04:00
Mai 94273fbf4f Merge pull request #2760 from Sonicadvance1/switch_to_half_barriers 
Arm64: Switch to using half barriers
 2023-07-27 09:07:14 -04:00
Alyssa Rosenzweig 0caf263c77 OpcodeDispatcher: Preserve PF across zero shifts 
Reported by CATFELLA on Discord. uwu

Fixes: 7e6bb04db ("OpcodeDispatcher: Extract CalculatePF")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-07-25 11:21:52 -04:00
Ryan Houdek 5821175ddb Merge pull request #2813 from Sonicadvance1/fix_ra_lr 
Arm64: Fixes LR corruption in 128-bit divides
 2023-07-24 15:08:45 -07:00
Alyssa Rosenzweig 27a1ebc2f5 IR: Expand to 16-bit opcodes 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-07-24 17:21:11 -04:00
Ryan Houdek 61e905a339 Arm64: Fixes LR corruption in 128-bit divides 
Need to save and restore LR before branching out to the helpers.
Confirmed that the rest of the JIT handles this correctly.
 2023-07-24 12:04:16 -07:00
Lioncache 10fdcaa109 Arm64/Emitter: Simplify SVE immediate shift helper 
We can collapse the entire if statement to be much simpler.
 2023-07-24 15:04:14 -04:00
Ryan Houdek ba672f868c Arm64: Switch to using half barriers 
Inspired from: https://github.com/dotnet/runtime/issues/8072

Currently FEX is /very/ heavy handed with our backpatching where we wrap
every backpatched loadstore with `dmb ish`.

This can be relaxed slightly according to the linked issue.

For TSO load instructions the instruction sequence changes to:
  ldr <args>;
  dmb ld; <-- Slightly less strict dmb

For TSO store instructions the instruction sequence changes to:
  dmb ish; <-- Still the all encompassing dmb
  str <args>;

For backpatching loadstores this does the same thing where only one side
needs the nop and it uses the same instruction sequence when
backpatched.

The minor change is that on load backpatching, we are no longer backing
up a single instruction, instead just re-executing the instruction we
patched directly.

Took a long time to come back to this (Last looked in August 2020).
Previously when I was implementing this idea it didn't work, but that
was because our CompareExchange operation was broken back then. With the
CAS now, it should just work.
 2023-07-24 11:06:20 -07:00
Lioncache 9c3a843df7 Arm64/Emitter: Move indexed dup handling into SVEDup 
SVEDup is only used by dup(), so we can move all the implementation
details into it instead of keeping it all in the public function.
 2023-07-24 13:53:57 -04:00
Lioncache 8defa2b55f Arm64/Emitter: Collapse encoding cases for indexed dup 
Lets us hoist out the asserts and also collapse all the
branching into one series of operations.
 2023-07-24 13:53:42 -04:00
Ryan Houdek 77c88ffe53 Merge pull request #2804 from alyssarosenzweig/eor-zero 
Optimize `xor %eax, %eax`
 2023-07-24 09:01:53 -07:00