steam-frame/FEX-Emu--FEX
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Code Issues Packages Projects Releases 67 Wiki Activity
4,925 Commits 11 Branches 71 Tags
80cf3ca6b911cdeff3ecc7de01f5eb20e16523ae
Commit Graph
1638 Commits
Author SHA1 Message Date
lioncash 80cf3ca6b9 IR: Handle 256-bit VUnZip 
Extends VUnZip to handle 256-bit vectors.
 2022-10-25 15:49:02 +00:00
Ryan Houdek ab45db1665 Merge pull request #2094 from lioncash/zip 
IR: Handle 256-bit VZip/VZip2
 2022-10-20 19:02:29 -07:00
Ryan Houdek bb38bcb67d Merge pull request #2093 from lioncash/shrn 
IR: Handle 256-bit VUShrNI/VUShrNI2
 2022-10-20 19:00:51 -07:00
lioncash 340b2ca624 IR: Handle 256-bit VZip2 
Extends VZip2 to handle 256-bit vectors.
 2022-10-20 21:15:18 +00:00
lioncash 5baa15de03 IR: Handle 256-bit VZip 
Extends VZip to handle 256-bit vectors.
 2022-10-20 19:22:07 +00:00
lioncash 6ddca804d1 IR: Handle 256-bit VUShrNI2 
Extends VUShrNI2 to handle 256-bit vectors.
 2022-10-20 18:31:36 +00:00
lioncash f9831a85fb IR: Handle 256-bit VUShrNI 
Extends VUShrNI to handle 256-bit vectors.
 2022-10-20 17:51:47 +00:00
lioncash 7261033b7f IR: Handle 256-bit VSQXTUN2 
Extends VSQXTUN2 to handle 256-bit vectors.
 2022-10-20 17:08:00 +00:00
lioncash 3ad6866198 IR: Handle 256-bit VSQXTUN 
Extends VSQXTUN to handle 256-bit vectors.
 2022-10-20 16:51:53 +00:00
Ryan Houdek 1c7d4165ab Merge pull request #2091 from lioncash/vsqxtn 
IR: Handle 256-bit VSQXTN/VSQXTN2
 2022-10-19 20:46:53 -07:00
lioncash 07be100daf IR: Handle 256-bit VSQXTN2 
Extends VSQXTN2 to handle 256-bit vectors.
 2022-10-20 02:41:45 +00:00
lioncash de9351eefb IR: Handle 256-bit VSQXTN 
Expands VSQXTN to handle 256-bit vectors.
 2022-10-20 02:04:05 +00:00
lioncash ad39add55f Arm64/VectorOps: Simplify VUXTL2 SVE implementation 
Turns out there's an instruction that does what we need, but isn't named
similarly to UXTL2 at all.
 2022-10-19 22:24:07 +00:00
lioncash f3c301e359 Arm64/VectorOps: Simplify VUXTL SVE implementation 
Turns out there's an instruction that does what we need, but has a name
not similar to UXTL
 2022-10-19 22:22:23 +00:00
lioncash 1c37a1b4d6 Arm64/VectorOps: Simplify VSXTL2 SVE implementation 
Turns out there's a built-in instruction that does exactly what we want,
but just has a different name from SXTL2
 2022-10-19 22:16:33 +00:00
lioncash 7222529904 Arm64/VectorOps: Simplify VSXTL SVE implementation 
Was reading the ARM ARM and realized there's an instruction that does
exactly what we need right out of the box.
 2022-10-19 22:12:22 +00:00
wannacu d4416d200e OpcodeDispatcher: Implements DAA, DAS, AAA, AAS, AAM and AAD instruction 2022-10-19 13:56:06 +08:00
Ryan Houdek 3ac5e0423a Merge pull request #2088 from lioncash/vsmull 
IR: Handle 256-bit VSMull/VSMull2
 2022-10-18 16:11:03 -07:00
Mai b1e475d81d Merge pull request #2081 from Sonicadvance1/fix_rotate_flags 
OpcodeDispatcher: Fixes flag calculation on ROR and ROL by immediate
 2022-10-18 22:33:47 +00:00
Mai 4a09a4324f Merge pull request #2082 from Sonicadvance1/fix_c2_fprem1 
OpcodeDispatcher: Fixes FPREM1 C2 flag calculation
 2022-10-18 22:33:29 +00:00
lioncash 47f94327c5 IR: Amend x86_64 32->64 case for VUMull2 
Realized I forgot to amend the registers used in the final multiply.
 2022-10-18 16:23:16 +00:00
lioncash a009ed0b6b IR: Handle 256-bit VSMull2 
Extends VSMull2 to handle 256-bit vectors.
 2022-10-18 16:23:14 +00:00
lioncash 2476a686e7 IR: Handle 256-bit VSMull 
Extends VSMull to handle 256-bit vectors.
 2022-10-18 16:22:44 +00:00
Ryan Houdek 78a077397e Merge pull request #2085 from lioncash/vmull 
IR: Handle 256-bit VUMull/VUMull2
 2022-10-17 18:10:48 -07:00
lioncash 0c4b456aaa IR: Handle 256-bit VUMull2 
Extends VUMull2 to handle 256-bit vectors.
 2022-10-17 19:03:26 +00:00
lioncash 09185167bc OpcodeDispatcher/Vector: Amend and simplify PMULLOp 
Allows PMULLOp to function correctly with the amended VPSHUFD entries.

Since this is only used to perform expanded multiplication from 32-bit
entries to 64-bit entries, we can simplify things a little bit.

All we need to do is yank the third 32-bit word down into the second
32-bit word's spot in the vector and let the VUMull/VSMull IR ops handle
it.
 2022-10-17 19:03:26 +00:00
lioncash 5d78c3203c IR: Handle 256-bit VUMull 
Extends VUMull to handle 256-bit vectors.

While we're at it, we can fix a typo in the VPSHUFD called for the
32->64-bit case.

To mirror UMULL, we need to replicate element 0 and 1, not 0 and 2

While we're at it, we can fix this with VSMull as well.
 2022-10-17 19:03:23 +00:00
Ryan Houdek 102d5c57cb OpcodeDispatcher: Fixes FPREM1 C2 flag calculation 
Accidentally didn't implement this for FPREM1 but it /was/ implemented
for FPREM. Fixes an infinite loop in cossin implementations.

Test code from the application returns an incorrect result, but it isn't
due to FPREM1.

```
$ `which wine` ./hello.exe
Sin 1.22460635382238E-16
Cos -1
$ FEXInterpreter `which wine` ./hello.exe
Sin 1.22460635382238E-16
Cos 0.54030230586814
```

Fixes #2021
 2022-10-16 15:24:46 -07:00
Ryan Houdek ffb4de9fd9 Merge pull request #2079 from Sonicadvance1/ensure_armemitter_uses_allocator 
Ensure Arm64Emitter uses FEX allocator
 2022-10-15 15:37:23 -07:00
Ryan Houdek 9b77e7fd13 OpcodeDispatcher: Fixes flag calculation on ROR and ROL by immediate 
These were being calculated incorrectly in the case of rotating with
values larger than 8-bit or 16-bit
 2022-10-14 23:36:48 -07:00
Ryan Houdek abb44d3327 Merge pull request #2069 from wannacu/main 
Flags: Refine _Bfe's shift
 2022-10-14 22:53:05 -07:00
Ryan Houdek 11eaf3d48a Ensure Arm64Emitter uses FEX allocator 
Otherwise we will end up allocating code buffers in the lower 32-bits,
consuming precious virtual address space.
 2022-10-14 22:04:07 -07:00
Ryan Houdek e9f3a5b3e4 Merge pull request #2074 from lioncash/vuxtl 
IR: Handle 256-bit VUXTL/VUXTL2
 2022-10-13 13:15:47 -07:00
Ryan Houdek ebc45dff45 Merge pull request #2070 from lioncash/vuabdl 
IR: Handle 256-bit VUABDL
 2022-10-13 12:17:47 -07:00
lioncash fc4a5ebfd3 IR: Handle 256-bit VUXTL2 
Extends VUXTL2 to handle 256-bit vectors.
 2022-10-13 19:15:05 +00:00
lioncash 1d7b688c55 IR: Handle 256-bit VUXTL 
Extends VUXTL to handle 256-bit values.
 2022-10-13 19:07:57 +00:00
lioncash 0436540791 IR: Handle 256-bit VSXTL2 
Extends VSXTL2 to handle 256-bit vectors.
 2022-10-13 18:21:25 +00:00
lioncash a87ac86e18 IR: Handle 256-bit VSXTL 
Extends VSXTL to handle 256-bit vectors.
 2022-10-13 18:21:22 +00:00
lioncash 02f5ea4b9d IR: Handle 256-bit VUABDL 
Extends VUABDL to handle 256-bit vectors.
 2022-10-13 15:37:10 +00:00
wannacu 2e14e613d0 Flags: Refine _Bfe's shift 2022-10-13 16:41:04 +08:00
lioncash 71043e372a IR: Handle 256-bit VSMul/VUMul 
Extends VSMul and VUMul to handle 256-bit vectors.
 2022-10-12 00:00:15 +00:00
lioncash 8fb03ff1b9 IR: Handle 256-bit VRev64 
Extends VRev64 to handle 256-bit vectors.
 2022-10-11 20:17:04 +00:00
Ryan Houdek c2b6aef6f4 Merge pull request #2065 from lioncash/shift-imm 
IR: Handle 256-bit VShlI/VUShlI/VUShrI
 2022-10-11 12:16:44 -07:00
lioncash 24547318c6 IR: Handle 256-bit VShlI 
Extends VShlI to handle 256-bit vectors.
 2022-10-11 18:19:23 +00:00
lioncash 48d1184066 IR: Handle 256-bit VSShrI 
Extends VSShrI to handle 256-bit vectors.
 2022-10-11 18:04:13 +00:00
lioncash 5ba510474b IR: Handle 256-bit VUShrI 
Extends VUShrI to handle 256-bit vectors.
 2022-10-11 17:08:35 +00:00
Ryan Houdek 51214d1be1 Merge pull request #2064 from lioncash/vushls 
IR: Handle 256-bit VSShrS/VUShlS/VUShrS
 2022-10-11 09:59:03 -07:00
lioncash 4721894427 IR: Handle 256-bit VSShrS 
Extends VSShrS to handle 256-bit vectors.
 2022-10-11 16:21:50 +00:00
lioncash d429865b6e IR: Handle 256-bit VUShrS 
Extends VUShrS to handle 256-bit vectors.
 2022-10-11 16:08:09 +00:00
lioncash ca5881a72c IR: Handle 256-bit VUShlS 
Extends VUShlS to handle 256-bit vectors.
 2022-10-11 15:45:39 +00:00