Lioncache
cc11de16bf
ASIMD_Tests: Enable PMULL/PMULL2 tests
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vixl now supports these. We can also get rid of the invalid data sizes,
since only halfword and 128-bit variants are defined.
2025-04-21 20:03:37 -04:00
Ryan Houdek
f912295690
Merge pull request #4524 from bylaws/faulto
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X86Tables: Set FLAGS_BLOCK_END for more faulting ops
2025-04-19 19:02:09 -07:00
Lioncache
4e6f183f77
CodeEmitter/LoadstoreOps: Add Load/store register (PAC) group
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Eh, what the heck. Gets rid of the last TODO marker in the base load-stores.
2025-04-19 13:00:00 -04:00
Billy Laws
30fefbd57d
X86Tables: Set FLAGS_BLOCK_END for more faulting ops
2025-04-19 14:19:19 +01:00
Ryan Houdek
3da6fc3972
Merge pull request #4518 from neobrain/refactor_warn_fixes
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JIT: Fix warning about unused variable
2025-04-18 09:24:49 -07:00
Lioncache
d71aca9e9b
CodeEmitter/LoadStoreOps: Add Memory Copy and Memory Set category
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Adds all of the memory facilities in FEAT_MOPS to the emitter.
2025-04-18 10:53:38 -04:00
Tony Wasserka
0fe28129a0
JIT: Fix warning about unused variable
2025-04-18 11:16:46 +02:00
Ryan Houdek
6f5588f71e
Merge pull request #4504 from pmatos/NoStrictAliasing
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Enable -fno-strict-aliasing
2025-04-17 17:27:33 -07:00
Lioncache
d7a08fc7d4
CodeEmitter/ASIMDOps: Support RADDHN{2}/RSUBHN{2}
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These are trivial enough to just drop right in.
2025-04-17 20:13:30 -04:00
LC
572d6e0395
Merge pull request #4509 from Sonicadvance1/in_the_twilight_of_the_pale_blue_moon
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A couple of barrier and timing fixes.
2025-04-17 17:30:03 -04:00
Lioncache
bafcc8762b
CodeEmitter/ScalarOps: Handle ASIMD scalar x indexed element group
2025-04-17 14:47:38 -04:00
Lioncache
6330b398a5
CodeEmitter/ScalarOps: Handle ASIMD scalar three same extra group
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These are trivial enough to drop in.
2025-04-17 08:09:42 -04:00
Ryan Houdek
73593ad4f1
Merge pull request #4499 from bylaws/x87fix
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OpcodeDispatcher: Mark NZCV as dirty when clobbering in FCOMIF64
2025-04-16 10:32:13 -07:00
Ryan Houdek
572a58ed27
Merge pull request #4512 from lioncash/internal
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Arm64: Mark several functions as internally linked
2025-04-16 10:31:06 -07:00
Lioncache
e6841ea46d
Arm64_stubs: Remove non-public functions
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These aren't exposed in the public interface anymore, so they can be removed.
2025-04-16 09:21:51 -04:00
Lioncache
edbfe45a20
Arm64: Mark several functions as internally linked
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These aren't directly used outside of the translation unit.
2025-04-16 09:16:44 -04:00
Lioncache
5f83e89be5
ASIMD_Tests: Re-enable tests disabled due to dissassembly bugs
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These issues seem to be resolved now.
2025-04-16 08:47:18 -04:00
Billy Laws
416267a238
OpcodeDispatcher: Safely clobber NZCV in FCOMIF64
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Also fix a small typo that broke the !flagm2 path.
2025-04-16 13:06:37 +01:00
Ryan Houdek
00f8181c3a
OpcodeDispatcher: Fix CPUID being a instruction fence
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It is common practice for games to use CPUID as an instruction barrier
for various reasons. Ensure that we respect this by adding support for
an instruction barrier.
2025-04-15 15:42:43 -07:00
Ryan Houdek
60565cc2ef
OpcodeDispatcher: Implement support for self-synchronizing cycle counter
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FEAT_ECV added a new synchronizing cycle counter instruction that
restrict speculation across the cycle counter access. Because it
restricts speculation, it effectively acts like an isb and load dsb.
Luckily for us, this actually matches behaviour for what rdtscp does, so
we can take advantage of it if the host supports FEAT_ECV.
2025-04-15 15:42:43 -07:00
Ryan Houdek
bfee39ae70
HostFeatures: Passthrough if the host supports ECV
2025-04-15 15:38:00 -07:00
Lioncache
222fcfd70e
CodeEmitter/ASIMDOps: Add crypto two-register SHA512 category
2025-04-15 11:48:30 -04:00
Lioncache
95c8a70ce6
CodeEmitter/ASIMDOps: Add crypto four-reg category
2025-04-15 11:41:07 -04:00
Lioncache
0f6bec4d5e
CodeEmitter/ASIMDOps: Add crypto three-reg SHA512 category
2025-04-15 11:31:00 -04:00
Lioncache
5fb0522c78
CodeEmitter/ASIMDOps: Add crypto three-reg imm2 category
2025-04-15 11:15:21 -04:00
Paulo Matos
cb972e165b
Fix cast in ValidateCode impl
2025-04-15 09:35:46 +02:00
Paulo Matos
fb319a352a
Enable -fno-strict-aliasing
2025-04-14 09:29:15 +02:00
Ryan Houdek
211bec65d2
Merge pull request #4492 from bylaws/badencodings
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Frontend: Be more tolerant of bad instruction encodings
2025-04-13 19:09:07 -07:00
Billy Laws
039aaae041
FEXCore: Add a pre-compilation frontend callback to SyscallHandler
2025-04-11 12:07:16 +01:00
Billy Laws
4fca8fb8e6
AllocatorHooks: Correctly restore the region protection in VirtualDontNeed
2025-04-11 12:07:16 +01:00
Billy Laws
9625201cbf
Frontend: Remove asserts on invalid instruction encodings
2025-04-11 12:06:01 +01:00
Billy Laws
a1c6378317
Frontend: Only accept POP opcodes with a 0 ModRM.reg field
2025-04-09 23:04:11 +01:00
Billy Laws
f064013b9a
Frontend: Enforce FLAGS_SF_MOD_MEM_ONLY/FLAGS_SF_MOD_REG_ONLY
2025-04-09 23:02:09 +01:00
Billy Laws
d4480c3566
X86Tables: Mark VMOVNTDQ as FLAGS_SF_MOD_MEM_ONLY
2025-04-09 23:01:26 +01:00
Billy Laws
b3a4de7aa8
X86Tables: Mark MASKMOVQ as FLAGS_SF_MOD_REG_ONLY
2025-04-09 23:01:26 +01:00
Billy Laws
60d8131a4d
X86Tables: Drop FLAGS_SF_MOD_MEM_ONLY from (V)MOV(L/H)PS
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These encodings are shared with MOVLHPS/MOVHLPS and FEX handles both variants.
2025-04-09 23:01:26 +01:00
Billy Laws
6d78aefa13
Frontend: Ignore REX register extension for MMX registers
2025-04-09 23:01:26 +01:00
Ryan Houdek
7ca757bb6d
FEXCore: Move CPUInfo to FEX
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This is only ever used in the frontend now.
2025-04-08 22:54:43 -07:00
Ryan Houdek
c2d59b02bd
FEXCore: Reduce stack usage in CalculateNumberOfCPUs
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Nothing crazy, just recalculate the maximum string length rather than
use PATH_MAX.
2025-04-08 22:54:43 -07:00
Ryan Houdek
5767c61a91
FEXCore/Emitter: Stop creating a vector on the heap
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In the Push/Pop CalleeSavedRegisters these vectors were getting created
on the heap, allocating memory and then just iterating them.
Just use a std::array which makes it stop allocating memory and saves
the number of instructions.
2025-04-08 18:36:47 -07:00
Ryan Houdek
4377603d7e
FEXCore/Allocator: Removes old workaround for kernel 4.17
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This was only used for working around our old CI machines and now that
our minimum kernel requirement is 5.15 this isn't required anymore.
2025-04-08 18:22:39 -07:00
Ryan Houdek
2d7f37386e
Softfloat: Remove warnings
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These precision warnings are no longer true!
2025-04-07 15:22:24 -07:00
Ryan Houdek
0fbb6aa02f
cephes: Rewrite to use softfloat-3e 128-bit
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And also use it at the same time, since the function signatures changed.
Instead of relying on the host libc math libraries for `long double` ALU
operations, rewrite the entire thing to use softfloat-3e fixed width
float128_t types.
This is a very invasive change in cephes but is a necessary requirement
for getting the precision we require in environments that map `long
double` to be the same as `double`, like Win32 and MacOS.
This fixes the precision issue in transcendental operations when running
under WINE.
2025-04-07 15:13:04 -07:00
Ryan Houdek
d8cd807520
Softfloat-3e: Moves to Externals
2025-04-05 17:26:15 -07:00
Ryan Houdek
ffca27cbde
FEXCore/Softfloat: Wire up cephes math library for transcendental operations
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This is solving a different problem than what #4411 is specifically
trying to solve.
For our transcendental operations, we can't currently guarantee that
these functions will actually operate at the 128-bit softfloat
precision. While this is true with glibc, this is /not/ true for musl
and likely more libraries.
Instead of relying on our libc implementation to implement these,
instead include the cephes math library directly which is what most
people use for this. Including musl even, but not for all operations.
With this we are no longer beholden to the standard libraries for
providing a correct implementation.
2025-04-04 16:03:09 -07:00
LC
74cb225ccb
Merge pull request #4478 from Sonicadvance1/sha256rnds2_for_reals
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OpcodeDispatcher: Implement support for sha256rnds2 using ARM instructions
2025-04-03 11:26:58 -04:00
LC
d5db2ccf18
Merge pull request #4475 from Sonicadvance1/x87_stack_bug
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x87OptimizationPass: Fixes {Inc,Dec}StackPop
2025-04-03 11:25:53 -04:00
Ryan Houdek
cebcf50c65
x87OptimizationPass: Fixes {Inc,Dec}StackPop
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On the slow path these were pushing and popping in the wrong direction.
Switch them around to ensure the unittests work.
2025-04-02 14:25:02 -07:00
Ryan Houdek
ec1c7797f4
OpcodeDispatcher: Implement support for sha256rnds2 using ARM instructions
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The big one.
2025-04-02 12:51:03 -07:00
Ryan Houdek
907fd6b04b
unittests/Emitter: Enable crypto tests since vixl supports them now.
2025-04-02 12:43:50 -07:00
Lioncache