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Code Issues Packages Projects Releases 67 Wiki Activity
9,029 Commits 11 Branches 71 Tags
ad0dd34412d253a408b7cf32e0b08af48dc038ff
Commit Graph
90 Commits
Author SHA1 Message Date
Alyssa Rosenzweig a70ea30c02 IR: add CondSubNZCV (ccmp) instruction 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 17:50:57 -04:00
Alyssa Rosenzweig 706065b0e2 OpcodeDispatcher: accelerate cmpxchg with flagm 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-30 14:12:59 -04:00
Alyssa Rosenzweig 9fd32f07cb JIT: preserve nzcv for the slow atomic path 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-30 14:12:59 -04:00
Alyssa Rosenzweig 2a9fcc6a66 Merge pull request #3492 from Sonicadvance1/implement_prefetch 
OpcodeDispatcher: Implement support for the various prefetch instructions
 2024-03-18 07:49:47 -04:00
Ryan Houdek cc635a54f8 IR: Implements support for prefetch operation 2024-03-12 21:19:50 -07:00
Alyssa Rosenzweig c99cbe6d0a JIT: switch DF representation 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-11 18:50:31 -04:00
Alyssa Rosenzweig 72edee7c6f IR: add SETF8/SETF16 ir ops 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-01 19:40:53 -04:00
Alyssa Rosenzweig 15db72ef60 IR: add Sbb, SbbWithFlags ops 
For fusing sbc+sbcs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-26 15:25:03 -04:00
Alyssa Rosenzweig 6994fc3a01 IR,OpcodeDispatcher,JIT: fuse adcs flags 
The usual tricks, also requires introducing a bare adc op to optimize adcs to,
but we wanted that anyway!

Also support a zero source, so we can calculate "foo + CF" in one instruction to
optimize the "lock adc" cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-25 10:49:32 -04:00
Alyssa Rosenzweig 8540332520 IR: add AddWithFlags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig 22ab7f2b3e IR: add SubWithFlags op (arm64 subs) 
with 8/16-bit handling to keep everything uniform.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-24 15:54:49 -04:00
Alyssa Rosenzweig d7ff1b78fb IR: handle 8/16-bit AddNZCV/SubNZCV 
we can do it more effectively than the current s/w lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-12 12:36:09 -04:00
Alyssa Rosenzweig 99660129f3 IR: implement AndWithFlags for 8/16-bit 
easier to deal with in the JIT

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-06 14:22:28 -04:00
Alyssa Rosenzweig 4790a7ba79 IR: add AndWithFlags 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-02-05 15:32:21 -04:00
Alyssa Rosenzweig 8e7906a665 IR: add UMaxV 
will be used to accelerate ptest

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-01-29 13:19:22 -04:00
Ryan Houdek d098545c20 FEXCore: Removes SRA option, it's now permanently enabled 2023-12-28 18:28:02 -08:00
Mai 3d2cbc5d08 Merge pull request #3317 from Sonicadvance1/fix_imul_flags2 
OpcodeDispatcher: Fixes flags generation in imul
 2023-12-19 11:43:21 -05:00
Ryan Houdek 0ede707e0b IR: Adds support for AddShift IR op 
This matches x86 SIB's operation of `scale * index + base`
 2023-12-15 13:08:06 -08:00
Ryan Houdek acdb4c7061 IR: Adds support for {S,U}Mull 
Lets us do a 32-bit multiply returning a 64-bit result, signed and
unsigned.
 2023-12-07 01:06:58 -08:00
Ryan Houdek 3b0aff5fb9 IR: Moves remaining NZCV operations to use DestSize 
Just like in #3305 but wasn't causing any known issues
 2023-12-02 15:40:51 -08:00
Ryan Houdek c6497fe32b JIT: Fixes crash in TestNZ 
In some situations TestNZ is generated with a constant that is using a
constant that can't fit inside of the tst instruction.

This was found in libGLX with virgl, crashing invalid instruction
generation and crashing steamwebhelper
 2023-12-02 14:57:57 -08:00
Alyssa Rosenzweig 094146d630 IR: add axflag 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-17 17:37:24 -04:00
Alyssa Rosenzweig 23c2a53683 OpcodeDispatcher: move fcmp flag fixup to dispatcher 
simpler *and* much faster

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-17 17:37:24 -04:00
Ryan Houdek c1d5fae018 Merge pull request #3273 from alyssarosenzweig/opt/shifts 
Optimize shifts/rotates
 2023-11-14 14:13:56 -08:00
Ryan Houdek 74b2548982 IR: Implement support for VUSHRAI IR op 
This matches Arm64 usra semantics. This instruction is useful for
implementing vector element rotate.
 2023-11-13 18:22:45 -08:00
Ryan Houdek f31656ec65 IR: Support sha1h and sha256u0 
These match our needs so wire them up
 2023-11-13 18:22:45 -08:00
Alyssa Rosenzweig 83fdd5720f IR: Add ccmn 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-13 22:05:02 -04:00
Alyssa Rosenzweig 205ba2ea13 IR: add shifted xor 
for rotates.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-13 21:21:01 -04:00
Alyssa Rosenzweig ff37177f4d IR: Remove AND(N)Z conditions 
Unused since TestNZ+NZCVSelect accomplishes the same and good riddance. Might
bring them back later for tbz/tbnz, but certainly not in this Selectful form.

(I added them when I thought we were going to RA the flags. With the more
effective static approach, we don't need this for that.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-12 17:32:24 -04:00
Alyssa Rosenzweig 157f95b08f IR: Extend TestNZ to two sources 
Unlock the power of AND.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-12 17:32:24 -04:00
Alyssa Rosenzweig 0de958be2a IR: Remove Abs 
Now unused. If we bring it back, it should be brought back as CSSC only. On
non-CSSC platforms, an explicit cmp + predicated neg can be better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-12 17:32:24 -04:00
Alyssa Rosenzweig 5eea68d6c6 IR: Support predicated Neg 
i.e. cneg. will be used for x87 hell op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-12 17:32:24 -04:00
Alyssa Rosenzweig 099c683a5a IR: Add FromNZCV mode to CondJump 
In this mode, rather than the branch comparing its arguments and then jumping
based on the result, the branch simply jumps by the native comparison based on
the NZCV value. This allows us to map x86 branches to arm64 branches 1:1.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-12 17:32:24 -04:00
Alyssa Rosenzweig 041199644c IR: Add NZCVSelect op 
This will replace Select soon, as it lets us take advantage of
NZCV-generating instructions and it doesn't clobber NZCV.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-10 09:04:42 -04:00
Alyssa Rosenzweig 1281145982 OpcodeDispatcher: Optimize popf 
mostly for easier debugging tbh

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Alyssa Rosenzweig 5336129b58 IR: Optimize sub/sbb 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Alyssa Rosenzweig 72fc2b522d IR: Optimize add/adc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Alyssa Rosenzweig b6f6c84790 IR: Optimize tests 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Alyssa Rosenzweig afdb8753ba IR: Remove some implicit flag clobbers 
Do it explicitly for sve-256 and punt on optimizing, so we avoid regressing code
gen otherwise.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Alyssa Rosenzweig f6a2e6739d IR: VCMPEQ doesn't clobber nzcv 
cmeq not cmpeq!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Alyssa Rosenzweig b3055523b4 IR: Switch to dedicated NZCV load/store 
Semantics differ markedly from the non-NZCV flags, splitting this out makes it a
lot easier to do things correctly imho. Gets the dest/src size correct
(important for spilling), as well as makes our existing opt passes skip this
which is needed for correctness at the moment anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-09 09:40:51 -04:00
Ryan Houdek 5103f2d92b Merge pull request #3247 from alyssarosenzweig/refactor/nzcv-prereq 
Preparatory patches for nzcv
 2023-11-01 14:07:14 -07:00
Alyssa Rosenzweig d75c0f2c50 IR: Add missing flag clobbers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-01 15:44:36 -04:00
Alyssa Rosenzweig a586d3823d IR: VFCMPEQ does not clobber flag 
Oversight.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-11-01 15:44:36 -04:00
Ryan Houdek e4d9c264d8 IR: Adds support for tbx 2023-10-31 20:06:45 -07:00
Mai 77d92872bc Merge pull request #3212 from Sonicadvance1/dpp_opt 
OpcodeDispatcher: Optimize 128-bit DPPS and DPPD
 2023-11-01 04:01:05 +01:00
Ryan Houdek 14e5ea1e22 Merge pull request #3230 from Sonicadvance1/optimize_atomic_fetch 
IR: Optimize unused result atomic fetch mop to just atomic mop
 2023-10-26 15:57:20 -07:00
Ryan Houdek 9db93a43dd IR: Adds comments that atomic op layout must match 
If the fetch and nonfetch versions mismatched then the DCE optimization
which changes the IR operation would break handily.

Add a comment as a reminder so if anyone touches this they will
understand.
 2023-10-26 15:40:55 -07:00
Ryan Houdek 8f0461cac8 IR: Adds support for non-fetch Atomci CLR and NEG 2023-10-25 21:00:04 -07:00
Ryan Houdek 20a54913bd IR: Support shifted imms in VectorImm 
We will want to use this in some cases.
 2023-10-25 19:27:00 -07:00