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Commit Graph
2276 Commits
Author SHA1 Message Date
Mai b1e475d81d Merge pull request #2081 from Sonicadvance1/fix_rotate_flags 
OpcodeDispatcher: Fixes flag calculation on ROR and ROL by immediate
 2022-10-18 22:33:47 +00:00
Mai 4a09a4324f Merge pull request #2082 from Sonicadvance1/fix_c2_fprem1 
OpcodeDispatcher: Fixes FPREM1 C2 flag calculation
 2022-10-18 22:33:29 +00:00
Ryan Houdek 78a077397e Merge pull request #2085 from lioncash/vmull 
IR: Handle 256-bit VUMull/VUMull2
 2022-10-17 18:10:48 -07:00
lioncash 0c4b456aaa IR: Handle 256-bit VUMull2 
Extends VUMull2 to handle 256-bit vectors.
 2022-10-17 19:03:26 +00:00
lioncash 09185167bc OpcodeDispatcher/Vector: Amend and simplify PMULLOp 
Allows PMULLOp to function correctly with the amended VPSHUFD entries.

Since this is only used to perform expanded multiplication from 32-bit
entries to 64-bit entries, we can simplify things a little bit.

All we need to do is yank the third 32-bit word down into the second
32-bit word's spot in the vector and let the VUMull/VSMull IR ops handle
it.
 2022-10-17 19:03:26 +00:00
lioncash 5d78c3203c IR: Handle 256-bit VUMull 
Extends VUMull to handle 256-bit vectors.

While we're at it, we can fix a typo in the VPSHUFD called for the
32->64-bit case.

To mirror UMULL, we need to replicate element 0 and 1, not 0 and 2

While we're at it, we can fix this with VSMull as well.
 2022-10-17 19:03:23 +00:00
Ryan Houdek 102d5c57cb OpcodeDispatcher: Fixes FPREM1 C2 flag calculation 
Accidentally didn't implement this for FPREM1 but it /was/ implemented
for FPREM. Fixes an infinite loop in cossin implementations.

Test code from the application returns an incorrect result, but it isn't
due to FPREM1.

```
$ `which wine` ./hello.exe
Sin 1.22460635382238E-16
Cos -1
$ FEXInterpreter `which wine` ./hello.exe
Sin 1.22460635382238E-16
Cos 0.54030230586814
```

Fixes #2021
 2022-10-16 15:24:46 -07:00
Ryan Houdek ffb4de9fd9 Merge pull request #2079 from Sonicadvance1/ensure_armemitter_uses_allocator 
Ensure Arm64Emitter uses FEX allocator
 2022-10-15 15:37:23 -07:00
Ryan Houdek 9b77e7fd13 OpcodeDispatcher: Fixes flag calculation on ROR and ROL by immediate 
These were being calculated incorrectly in the case of rotating with
values larger than 8-bit or 16-bit
 2022-10-14 23:36:48 -07:00
Ryan Houdek abb44d3327 Merge pull request #2069 from wannacu/main 
Flags: Refine _Bfe's shift
 2022-10-14 22:53:05 -07:00
Ryan Houdek 11eaf3d48a Ensure Arm64Emitter uses FEX allocator 
Otherwise we will end up allocating code buffers in the lower 32-bits,
consuming precious virtual address space.
 2022-10-14 22:04:07 -07:00
Ryan Houdek e9f3a5b3e4 Merge pull request #2074 from lioncash/vuxtl 
IR: Handle 256-bit VUXTL/VUXTL2
 2022-10-13 13:15:47 -07:00
Ryan Houdek ebc45dff45 Merge pull request #2070 from lioncash/vuabdl 
IR: Handle 256-bit VUABDL
 2022-10-13 12:17:47 -07:00
lioncash fc4a5ebfd3 IR: Handle 256-bit VUXTL2 
Extends VUXTL2 to handle 256-bit vectors.
 2022-10-13 19:15:05 +00:00
lioncash 1d7b688c55 IR: Handle 256-bit VUXTL 
Extends VUXTL to handle 256-bit values.
 2022-10-13 19:07:57 +00:00
lioncash 0436540791 IR: Handle 256-bit VSXTL2 
Extends VSXTL2 to handle 256-bit vectors.
 2022-10-13 18:21:25 +00:00
lioncash a87ac86e18 IR: Handle 256-bit VSXTL 
Extends VSXTL to handle 256-bit vectors.
 2022-10-13 18:21:22 +00:00
lioncash 02f5ea4b9d IR: Handle 256-bit VUABDL 
Extends VUABDL to handle 256-bit vectors.
 2022-10-13 15:37:10 +00:00
wannacu 2e14e613d0 Flags: Refine _Bfe's shift 2022-10-13 16:41:04 +08:00
lioncash 71043e372a IR: Handle 256-bit VSMul/VUMul 
Extends VSMul and VUMul to handle 256-bit vectors.
 2022-10-12 00:00:15 +00:00
lioncash 8fb03ff1b9 IR: Handle 256-bit VRev64 
Extends VRev64 to handle 256-bit vectors.
 2022-10-11 20:17:04 +00:00
Ryan Houdek c2b6aef6f4 Merge pull request #2065 from lioncash/shift-imm 
IR: Handle 256-bit VShlI/VUShlI/VUShrI
 2022-10-11 12:16:44 -07:00
lioncash 24547318c6 IR: Handle 256-bit VShlI 
Extends VShlI to handle 256-bit vectors.
 2022-10-11 18:19:23 +00:00
lioncash 48d1184066 IR: Handle 256-bit VSShrI 
Extends VSShrI to handle 256-bit vectors.
 2022-10-11 18:04:13 +00:00
Ryan Houdek 8da9ebc2e0 Merge pull request #2062 from wannacu/main 
SMC: Fix possible deadlock
 2022-10-11 10:13:02 -07:00
lioncash 5ba510474b IR: Handle 256-bit VUShrI 
Extends VUShrI to handle 256-bit vectors.
 2022-10-11 17:08:35 +00:00
Ryan Houdek 51214d1be1 Merge pull request #2064 from lioncash/vushls 
IR: Handle 256-bit VSShrS/VUShlS/VUShrS
 2022-10-11 09:59:03 -07:00
lioncash 4721894427 IR: Handle 256-bit VSShrS 
Extends VSShrS to handle 256-bit vectors.
 2022-10-11 16:21:50 +00:00
lioncash d429865b6e IR: Handle 256-bit VUShrS 
Extends VUShrS to handle 256-bit vectors.
 2022-10-11 16:08:09 +00:00
lioncash ca5881a72c IR: Handle 256-bit VUShlS 
Extends VUShlS to handle 256-bit vectors.
 2022-10-11 15:45:39 +00:00
lioncash 7151b9daff Interpreter/VectorOps: Remove lingering magic 32 constants 
Makes these functions consistent with the rest that explicitly test for
256 bit width.
 2022-10-11 15:02:41 +00:00
lioncash d9b5e28b22 Interpreter: Handle 256-bit VSShr 
This is only implemented in the interpreter, so this is trivial.
 2022-10-11 14:58:40 +00:00
lioncash aa7954a7d6 Interpreter: Handle 256-bit VUShr 
This is only implemented in the interpreter, so this is trivial.
 2022-10-11 14:56:19 +00:00
lioncash 802c70d1ab Interpreter: Handle 256-bit VUShl 
This is only implemented in the interpreter, so this is trivial.
 2022-10-11 14:55:17 +00:00
wannacu 8f905988e9 Use compatible syscall helpers 2022-10-11 16:35:17 +08:00
Ryan Houdek 235e2b6c2c FEXCore/Allocator: Store what the host VA is 
Calling this function multiple times without this will change the
result.

Necessary so we can determine what the host VA is  from multiple
locations.
 2022-10-10 08:35:40 -07:00
lioncash c7ad066987 IR: Handle 256-bit VFCMPUNO 
Extends VFCMPUNO to handle 256-bit vectors.
 2022-10-06 15:43:01 +00:00
lioncash f4d229f1ba IR: Handle 256-bit VFCMPORD 
Extends VFCMPORD to handle 256-bit vectors.
 2022-10-06 15:33:30 +00:00
Ryan Houdek 25a8a00771 Merge pull request #2050 from lioncash/vfcmplt 
IR: Handle 256-bit VFCMPLT/VFCMPGT/VFCMPLE
 2022-10-04 14:44:54 -07:00
Ryan Houdek a67f7422b2 Merge pull request #2049 from lioncash/fcmeq 
IR: Handle 256-bit VFCMPEQ/VFCMPNEQ
 2022-10-04 14:43:52 -07:00
Ryan Houdek ed8150cfb6 Merge pull request #2048 from lioncash/vcmpgt 
IR: Handle 256-bit VCMPGT/VCMPGTZ/VCMPLTZ
 2022-10-04 14:42:53 -07:00
Ryan Houdek 462a163ba7 Merge pull request #2047 from lioncash/vcmpeq 
IR: Handle 256-bit VCMPEQ/VCMPEQZ
 2022-10-04 14:40:48 -07:00
lioncash 280b15ba2a IR: Handle 256-bit VFCMPLE 
Extends VFCMPLE to handle 256-bit vectors.
 2022-10-04 19:56:59 +00:00
lioncash 2a0b488e99 IR: Handle 256-bit VFCMPGT 
Extends VFCMPGT to handle 256-bit vectors.
 2022-10-04 19:43:32 +00:00
lioncash 3ef7c4ab51 IR: Handle 256-bit VFCMPLT 
Extends VFCMPLT to handle 256-bit vectors.
 2022-10-04 19:29:36 +00:00
lioncash e72d746036 IR: Handle 256-bit VFCMPNEQ 
Extends VFCMPNEQ to handle 256-bit vectors.
 2022-10-04 19:02:20 +00:00
lioncash 0bb4091e34 IR: Handle 256-bit VFCMPEQ 
Extends VFCMPEQ to handle 256-bit vectors.
 2022-10-04 18:44:12 +00:00
lioncash 6822fc595c IR: Handle 256-bit VCMPLTZ 
Extends VCMPLTZ to handle 256-bit vectors.
 2022-10-04 18:09:39 +00:00
lioncash a506a589dd IR: Handle 256-bit VCMPGTZ 
Extends VCMPGTZ to handle 256-bit vectors.
 2022-10-04 17:55:03 +00:00
lioncash 684a5977dd IR: Handle 256-bit VCMPGT 
Extends VCMPGT to handle 256-bit registers.
 2022-10-04 17:38:20 +00:00