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Author SHA1 Message Date
Ryan Houdek 4d98c890e7 Merge pull request #708 from Sonicadvance1/decode_tsx 
Add TSX names to decode tables so we know what they are
 2021-01-26 02:24:47 -08:00
Ryan Houdek 513cb27825 Add TSX names to decode tables so we know what they are 
Rather than just stating UND

We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
 2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis 29a8fd0a4a Tests: Add gcc-target-tests for 32 and 64 bit 2021-01-26 12:00:45 +02:00
Stefanos Kornilios Mitsis Poiitidis e466dfb480 Merge pull request #707 from Sonicadvance1/update_gvisor_tests 
Updates gvisor test results that have changed due to OS update
 2021-01-26 11:59:38 +02:00
Ryan Houdek 8cbfef2e74 Updates gvisor test results that have changed due to OS update 2021-01-26 01:11:40 -08:00
Stefanos Kornilios Mitsis Poiitidis 53582fdf47 Merge pull request #701 from FEX-Emu/skmp/opdisp-32-bit-fixes 
OpDisp: Address most 32-bit rip size issues
 2021-01-25 15:31:55 +02:00
Stefanos Kornilios Mitsis Poiitidis b0365871b6 OpDisp: Address most 32-bit rip size issues 2021-01-25 15:04:12 +02:00
Ryan Houdek 2721418fb7 Merge pull request #698 from phire/better_defaults 
Better Default Configuration
 2021-01-22 16:56:29 -08:00
Scott Mansell 3cae0a0932 Better Default Configuration 
Make FEX have good performance out of the box

resolves #685
 2021-01-23 13:47:53 +13:00
Ryan Houdek d4ffea5c31 Merge pull request #670 from FEX-Emu/skmp/faster-ra 
IR: Optimize runtime of optimization passes
 2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis 0546da7a75 Address review feedback 2021-01-22 11:01:36 +02:00
Ryan Houdek ce1b9fcdc9 Merge pull request #674 from FEX-Emu/skmp/split-irparser 
IR: Split parser from IRLoader, add IR::Parse(), Fixes, Tests
 2021-01-21 23:09:53 -08:00
Stefanos Kornilios Mitsis Poiitidis 8b025d4c26 IRLoader: Actually set EntryRIP if the IR was parsed 2021-01-21 22:19:16 +02:00
Stefanos Kornilios Mitsis Poiitidis e7f2a650b5 Fix compilation 2021-01-21 22:18:48 +02:00
Stefanos Kornilios Mitsis Poiitidis 3bd8731b26 IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner 2021-01-21 21:38:41 +02:00
Stefanos Kornilios Mitsis Poiitidis 13613c6de1 IR: Change ValidateCode to use two uint64_t instead of __uint128_t 2021-01-21 21:37:58 +02:00
Stefanos Kornilios Mitsis Poiitidis 1177c375ff IR: Further parser cleanups, add fence types 2021-01-21 21:17:27 +02:00
Stefanos Kornilios Mitsis Poiitidis fb57e5183a IR: Fix TypeDefinition to actually fit used vector sizes 2021-01-21 21:10:11 +02:00
Stefanos Kornilios Mitsis Poiitidis 74160f38c4 IR: Fix IREmitter::Copy 2021-01-21 21:01:27 +02:00
Stefanos Kornilios Mitsis Poiitidis 072067b5fd IR: Split parser from IRLoader, add IR::Parse() 2021-01-21 19:17:51 +02:00
Stefanos Kornilios Mitsis Poiitidis 773e5866b4 Merge pull request #666 from Sonicadvance1/handle_unaligned_caspal32 
Handle unaligned cmpxchg and cmpxchg8b on ARMv8.1+
 2021-01-21 13:30:18 +02:00
Stefanos Kornilios Mitsis Poiitidis 00ca576644 IRCompaction: Only memset in debug 2021-01-21 13:06:43 +02:00
Ryan Houdek 5226f779c3 Merge pull request #673 from FEX-Emu/skmp/fix-ir-printing 
IR: Fix Printing and Parsing for float conds
 2021-01-21 00:28:50 -08:00
Stefanos Kornilios Mitsis Poiitidis 036771d825 IR: Fix Printing and Parsing for float conds 2021-01-21 10:16:08 +02:00
Ryan Houdek 633ea045e5 Handles unaligned cmpxchg/cmpxchg8b in SIGBUS handler 
cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means
applications rely on unaligned behaviour support with it.

Steam relies on this to work for a linked list array of jobs in some
internal job queueing system. It will end up always aligning by offsets
of 4 since it stores a couple of pointers.

Doesn't currently support the case of unaligned cmpxchg8b crossing a
cacheline, which ends up being semi-broken depending on which x86
behaviour the application is expected.
Intel CPUs do the "Big ring lock" or "split locks". Which means accesses
across cachelines are atomic.
AMD CPUs will tear the value across the cacheline, which is expected x86
behaviour by spec.

If they are expecting Intel behaviour, then that application is just
broken on non-Intel platforms unless they are fine with a tear.
 2021-01-20 16:07:50 -08:00
Stefanos Kornilios Mitsis Poiitidis 0e7db64ac7 RA: Run compation after spilling, not before 2021-01-21 01:01:02 +02:00
Stefanos Kornilios Mitsis Poiitidis ac1036ac92 IR: Sync Invalid class with RA 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 9c462eb400 ConsProp: Revert to ordered set for identical codegen 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 8aef9cb6a7 RA: Exit after first spill per iteration is found 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis d3fc85e18d RA: Make spans at least 1 offset long 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 9f3ce47917 RA: Expire ending intervals before starting new ones 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis a9332e604a JIT/x64: Fix VAddV 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis e7e6b6654f RA: Cleanups 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis c3682f9a3b RA: Fix several bugs, get rid of virtual registers, remove unused complexity 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 47ee9af96c ConstProp: Keep pools in heap 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 10b6fb02c4 RA: Rename CalculatePrecessors to CalculatePredecessors 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 9c760ff83b RA: Get OP_JUMP/CONDJUMP without loop in CalculatePrecessors 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis f3e19ef015 DSE: No need to loop to find branching op 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 6bdf785223 DSE: Optimize map lookups 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 997650bafc DSE: Merge logic more for perf 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 56ca73191d DSE: Merge Flag/GPR/FPR passes for perf 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 900fc6d2a7 ConstProp: Switch maps to unordred_maps 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis af94e24ba3 RA: Simplify and optimize data structures 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 6380ab6bfd RA: Optimize register conflict handling 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 91ddc1dd38 RCLSE: Optimize FindMemberInfo to be O(1) 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis 77d072e35c RA: Switch active set to also use BucketList 2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis e847f94b69 RA: rework ConstrainedRAPass::CalculateNodeInterference 2021-01-20 04:26:06 +02:00
Ryan Houdek eb6386b921 Merge pull request #671 from FEX-Emu/skmp/ir-prettyprint 
IR: Pretty print %Invalid, don't print invalid regs
 2021-01-19 18:17:43 -08:00
Stefanos Kornilios Mitsis Poiitidis c42c57af35 IR: Pretty print %Invalid, don't print invalid regs 2021-01-20 04:06:37 +02:00
Stefanos Kornilios Mitsis Poiitidis 814ca4746b Merge pull request #669 from Sonicadvance1/workaround_llvm_native 
Works around Clang failing to identify new Kryo CPUs
 2021-01-20 03:48:55 +02:00