We want to see the output from all of our runners.
Usually the x86 runner quickly spins through things and then we never see the ARM results if that side failed.
When RA made the source address register be the same register as the
destination register then we could have overwritten the address with the
move.
Use a temporary until we get RA constraints in place.
For loadstores to memory, this will use TSO ops to emulate x86
behaviour.
In the case that the source register is the stack pointer then it falls
back down to using regular loadstores. Since it is expected that stack
pointer usage will be thread specific.
With the AArch64 implementation this makes us be quite a bit closer to
being x86 TSO compliant
This patches unaligned LORegion loadstores with DMB wrapped loadstores.
This will ensure full cacheline consistency on loadstores, at the
expense of speed.
The performance can potentially be improved with "Half-barriers"
Described a bit here: https://github.com/dotnet/runtime/issues/8072
We can worry about that path after the initial implementation
This is the base implementation that uses LORegion loadstore
instructions to support the load/store release semantics, which these
instructions use.
Sadly these don't match the alignment requirements of x86 loadstores, so
if it was just used everywhere then it will cause alignment faults.
This means we need to catch the sigbus and backpatch the instruction to
do safe (aka expensive) TSO.
Currently this backpatch just falls back to regular loadstores
surrounded by DMB instructions.
Basically unaligned loadstores will fall back to nearly what we are
doing now, so significantly improved but not perfect.
A follow up PR will change this over to using a helper routine to be
100% safe
Behaviour now doesn't match between x86-64 and AArch64 so these need to
be disabled explicitly.
Once signaling is fully polished off then they can be reenabled for
x86-64 as well
It needs to track guest SigAltAction and have its own definitions for
sigaction and sa_mask. sa_mask specifically is defined differently
between the kernel and glibc.
Also fixes some issues with the SignalDelegator that posix tests found
We are rebranding an x86-64 illegal instruction near VIA's old ALTINST
instruction as an instruction to handle returning from guest signals
cleanly.
If this ever collides with a new x86-64 (unlikely) then we will need to
change the instruction.
This ends up looking similar to what we will do for thunk callbacks
Just generates some context level x86 code space for our guest to jump
in to.
This is only currently used for sigret but will become more important as
we come to support vdso.
Ryan Houdek