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Author SHA1 Message Date
Ryan Houdek c87c04db59 ARMEmitter: Implement cmn alias 
Inspired by #2832, since it was using adds directly.
cmn is an alias of adds with the destination register being zr.
 2023-07-28 13:58:23 -07:00
Ryan Houdek f5262446a0 Merge pull request #2833 from Sonicadvance1/remove_erroneous_asserts 
FEXCore: Remove erroneous asserts in the project
 2023-07-28 13:53:42 -07:00
Ryan Houdek 0a1820d444 Merge pull request #2834 from lioncash/sveops 
Arm64/Emitter: Deduplicate some more SVE implementations pt. 2
 2023-07-28 13:50:12 -07:00
Ryan Houdek a255813e99 FEXCore: Remove erroneous asserts in the project 
Inspired by #2832 by going through the source and removing uses of
`assert`.

assert doesn't work for us in debug builds because some games will
capture SIGABRT and continue running. So we need to use FEX's built in
assert handlers which call `FEX_TRAP_EXECUTION` which will take down the
FEX process as expected.

There wasn't too much usage of this in the source, so this is relatively
straightforward.
 2023-07-28 13:36:05 -07:00
Lioncache 4c6336b560 Arm64/Emitter: Simplify load/store contiguous (scalar plus scalar) group 
Lets us move the base opcode into the implementing function.
While we're at it, we can also add an assert to enforce predicate ranges.
 2023-07-28 16:30:34 -04:00
Lioncache 145c7799a5 Arm64/Emitter: Simplify load/store contiguous (scalar plus immediate) group 
We can move asserts and the base opcode into the implementing function.
While we're at it, we can add an assert to ensure predicate registers are in range.
 2023-07-28 16:30:34 -04:00
Lioncache 91df503e55 Arm64/Emitter: Simplify load/store multiple contiguous (scalar plus immediate) group 
We can centralize the base opcode and some of the asserts in the implementing function.
We can also add an assert that validates the predicate register range
and also make the offset assertions much more informative.
 2023-07-28 16:30:30 -04:00
Lioncache 3c417cee84 Arm64/Emitter: Reduce qualifying in SVE FP/Int Convert To FP/Int groups 
Since everything we need is already in the ARMEmitter namespace, we
don't need to qualify all type usages, which reduces the verbosity
a little during reading.
 2023-07-28 14:57:43 -04:00
Lioncache 857780b46e Arm64/Emitter: Fix sorting of SVE integer to float group 
This is actually already implemented but was grouped with the
SVE floating-point convert to integer group. We can extract this
out to be organized a little nicer.
 2023-07-28 14:52:57 -04:00
Lioncache cb34aa3dee Arm64/Emitter: Simplify SVE FP/Int Convert To FP/Int groups 
We can move the base opcode and asserts into the implementing function.
We can also add an assert to ensure the predicate is in a valid range.
 2023-07-28 14:44:54 -04:00
Lioncache 0d74777954 Arm64/Emitter: Simplify SVE FP Unary Operations Predicated group 
We can move the op into the implementing function and get rid of
an unnecessary function.

We can also add an assert to ensure the predicates are valid as well.
 2023-07-28 14:24:28 -04:00
Ryan Houdek 092a023900 OpcodeDispatcher: Use VZip to make merge more optimal in PSAD 
Thanks to @dougallj for noticing this.
Fixes #2818

New ASM
```asm
0x00007fffe2080808  10ffffe0            adr x0, #-0x4 (addr 0x7fffe2080804)
0x00007fffe208080c  f9005f80            str x0, [x28, #184]
0x00007fffe2080810  3dc03cc4            ldr q4, [x6, #240]
0x00007fffe2080814  2e247305            uabdl v5.8h, v24.8b, v4.8b
0x00007fffe2080818  6e247304            uabdl2 v4.8h, v24.16b, v4.16b
0x00007fffe208081c  4e71b8a5            addv h5, v5.8h
0x00007fffe2080820  4e71b884            addv h4, v4.8h
0x00007fffe2080824  4ec438b8            zip1 v24.2d, v5.2d, v4.2d
0x00007fffe2080828  58000040            ldr x0, pc+8 (addr 0x7fffe2080830)
0x00007fffe208082c  d63f0000            blr x0
```
 2023-07-28 10:56:59 -07:00
Ryan Houdek b57dd5c3aa OpcodeDispatcher: Optimize PSAD* to use vuabdl{2,} 
Optimizes this instruction from 18 down to 12 instructions.

Still has some extraneous moves at the tail of the operation that don't need to exist.

Before:
```asm
0x00007fffe2080908  10ffffe0            adr x0, #-0x4 (addr 0x7fffe2080904)
0x00007fffe208090c  f9005f80            str x0, [x28, #184]
0x00007fffe2080910  3dc03cc4            ldr q4, [x6, #240]
0x00007fffe2080914  2f08a705            uxtl v5.8h, v24.8b
0x00007fffe2080918  6f08a706            uxtl2 v6.8h, v24.16b
0x00007fffe208091c  2f08a487            uxtl v7.8h, v4.8b
0x00007fffe2080920  6f08a484            uxtl2 v4.8h, v4.16b
0x00007fffe2080924  6e6784a5            sub v5.8h, v5.8h, v7.8h
0x00007fffe2080928  6e6484c4            sub v4.8h, v6.8h, v4.8h
0x00007fffe208092c  4e60b8a5            abs v5.8h, v5.8h
0x00007fffe2080930  4e60b884            abs v4.8h, v4.8h
0x00007fffe2080934  4e71b8a5            addv h5, v5.8h
0x00007fffe2080938  4e71b884            addv h4, v4.8h
0x00007fffe208093c  4ea51ca0            mov v0.16b, v5.16b
0x00007fffe2080940  6e180480            mov v0.d[1], v4.d[0]
0x00007fffe2080944  4ea01c18            mov v24.16b, v0.16b
0x00007fffe2080948  58000040            ldr x0, pc+8 (addr 0x7fffe2080950)
0x00007fffe208094c  d63f0000            blr x0
```

After:
```asm
0x00007fffe2080848  10ffffe0            adr x0, #-0x4 (addr 0x7fffe2080844)
0x00007fffe208084c  f9005f80            str x0, [x28, #184]
0x00007fffe2080850  3dc03cc4            ldr q4, [x6, #240]
0x00007fffe2080854  2e247305            uabdl v5.8h, v24.8b, v4.8b
0x00007fffe2080858  6e247304            uabdl2 v4.8h, v24.16b, v4.16b
0x00007fffe208085c  4e71b8a5            addv h5, v5.8h
0x00007fffe2080860  4e71b884            addv h4, v4.8h
0x00007fffe2080864  4ea51ca0            mov v0.16b, v5.16b
0x00007fffe2080868  6e180480            mov v0.d[1], v4.d[0]
0x00007fffe208086c  4ea01c18            mov v24.16b, v0.16b
0x00007fffe2080870  58000040            ldr x0, pc+8 (addr 0x7fffe2080878)
0x00007fffe2080874  d63f0000            blr x0
```
 2023-07-28 10:56:59 -07:00
Ryan Houdek 0bea508935 IR: Adds support for VUABDL2 operation 
FEX already supported VUABDL, but we had missed VUABDL2.
 2023-07-28 10:56:59 -07:00
Ryan Houdek 9c175da0e2 Merge pull request #2831 from lioncash/moreop 
Arm64/Emitter: Deduplicate some more SVE implementations
 2023-07-28 10:47:50 -07:00
Lioncache cc359f09ad Arm64/Emitter: Simplify SVE FP convert precision odd elements 
We can move the base opcode into the implementation function.
We can also add an assert to ensure that the predicate is in a valid range.
 2023-07-28 13:34:04 -04:00
Lioncache dedeba0575 Arm64/Emitter: Simplify SVE2 Character Match group 
We can move the base opcode into the implementation function.
 2023-07-28 13:34:04 -04:00
Lioncache dc3ccbcc43 Arm64/Emitter: Simplify SVE SEL instruction 
We can move the base opcode and asserts into the implementing function.
We can also implement the mov alias in terms of sel()
 2023-07-28 13:34:04 -04:00
Lioncache ebd9b49dbe Arm64/Emitter: Simplify SVE2 bitwise ternary operations category 
We can move the asserts into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache 43e21ad749 Arm64/Emitter: Simplify SVE permute vector elements category 
We can move the asserts and the base opcode into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache 1b3beec085 Arm64/Emitter: Add missing SVE TBL encoding 
Adds the missing SVE2 double table encoding.

Crosses off a TODO.
 2023-07-28 13:34:04 -04:00
Lioncache c88f2e0730 Arm64/Emitter: Simplify SVE table lookup category 
We can move the base opcode into the implementing function.
 2023-07-28 13:34:04 -04:00
Lioncache 1645f6e582 Arm64/Emitter: Simplify SVE integer add/sub vectors unpredicated category 
We can move the base op encoding into the implementing function.
 2023-07-28 13:34:04 -04:00
Mai af35e18979 Merge pull request #2830 from Sonicadvance1/fix_smc_race 
FEXLinuxTests: Fixes race in smc-mt-2
 2023-07-28 13:23:08 -04:00
Ryan Houdek 012c0ae062 FEXLinuxTests: Fixes race in smc-mt-2 
This test was written to test SMC where one thread is doing execution
while the other thread is modifying.

According to the printf documentation it is supposed to "wait for code
to be modified" but actually it was testing a race between a printf on
one thread and the primary thread modifying the code.

Fix this test so it is actually waiting for code modification to happen
rather than testing a race condition. This is likely what the original
author intended.

CI is hitting this flake more frequently now because it is even faster
it seems, so fixing this test is necessary to resolve these flakes.
 2023-07-27 19:24:57 -07:00
Ryan Houdek dc8f063a4b Merge pull request #2823 from Sonicadvance1/fix_mingw_build 
Mingw: Fixes compiling again
 2023-07-27 18:14:07 -07:00
Ryan Houdek 759747b3c5 Merge pull request #2828 from lioncash/unused 
LongDivideRemovalPass: Remove unused variable
 2023-07-27 16:27:56 -07:00
Lioncache 4c6d26f167 LongDivideRemovalPass: Remove unused variable 2023-07-27 19:13:29 -04:00
Ryan Houdek 7562ff2308 Merge pull request #2827 from lioncash/alias 
Context: Pull out some long std::function declarations into aliases
 2023-07-27 16:11:20 -07:00
Lioncache e2baa1106b Context: Make alias for code invalidation functor 
Makes it so any changes wouldn't need to go across everything implementing the Context class.
 2023-07-27 18:59:15 -04:00
Lioncache 68880fd66b Context: Make alias for custom IR handlers 
Puts the type declaration in one place.
 2023-07-27 18:43:19 -04:00
Lioncache 62eef6c548 AOTIR: std::move function instances where applicable 
Ensures no unnecessary allocations occur.
 2023-07-27 18:35:30 -04:00
Lioncache cfdc1bda47 AOTIR: Add aliases for long functors 
Puts the really long declarations in one spot, which makes them
nicer to change over time.
 2023-07-27 18:30:07 -04:00
Ryan Houdek f9a9645ef3 Merge pull request #2826 from lioncash/unused 
Frontend: Remove unused ModRMDecoded instance
 2023-07-27 14:30:19 -07:00
Lioncache 8fc903cc51 Frontend: Remove unused ModRMDecoded instance 
This is assigned to but never used.
 2023-07-27 17:18:16 -04:00
Ryan Houdek c81b1c3432 Merge pull request #2825 from lioncash/lookup 
Frontend: Remove redundant lookups in BranchTargetInMultiblockRange()
 2023-07-27 14:00:40 -07:00
Lioncache db9ba16a53 Frontend: Remove redundant lookups in BranchTargetInMultiblockRange() 
insert() will only ever perform an insertion if the relevant element
doesn't exist within the set, so we were doing an unnecessary lookup
in two spots.

We don't use emplace() here because it will need to construct the
key for the element inside the allocated node (since the key may
be non-copyable/non-movable), causing an allocation even if an insert
doesn't actually occur.

Conversely, insert() will not need to allocate and construct a node
ahead of time if an element already exists in the set.
 2023-07-27 16:28:37 -04:00
Ryan Houdek 0be68a54d0 Merge pull request #2824 from lioncash/opsimp 
Arm64/Emitter: Reorganize some base opcode and assert locations
 2023-07-27 13:18:23 -07:00
Lioncache 6e140e9ff2 Arm64/Emitter: Simplify SVE Integer Compare With Unsigned Immediate category 
We can move the asserts into the implementation function.
 2023-07-27 14:12:16 -04:00
Lioncache d793f7295a Arm64/Emitter: Add missing cmpne signed immediate op 
Noticed while simplifying the signed immediate implementation.
 2023-07-27 14:08:26 -04:00
Lioncache 8f6018a1b4 Arm64/Emitter: Simplify SVE Integer Compare With Signed Immediate category 
We can move all asserts and handling into the implementation function.
 2023-07-27 14:03:34 -04:00
Lioncache 0a97d4456d Arm64/Emitter: Simplify SVE Predicate Logical Operations category 
We can move the base opcode into the implementation function.
 2023-07-27 13:51:48 -04:00
Lioncache c2dbe8309b Arm64/Emitter: Simplify SVE Bitwise Logical Operations Predicated category 
We can move the asserts and base opcode into the implementation function.
We can also add an assert to ensure a valid predicate range.
 2023-07-27 13:41:49 -04:00
Lioncache 06d66a0188 Arm64/Emitter: Simplify SVE Integer Mul/Div Vectors Predicated category 
We can move the base opcode into the implementation function.
We can also move the division assert into it as well.
 2023-07-27 13:36:22 -04:00
Lioncache ef254da7ca Arm64/Emitter: Simplify SVE Integer Min/Max/Difference Predicated category 
We can move the asserts into the implementation function and also add
another assert to validate the predicate range.
 2023-07-27 13:29:15 -04:00
Lioncache 162dcf3cd0 Arm64/Emitter: Simplify SVE Integer Add/Sub Vectors Predicated category 
We can move the opcode into the implementation function.
 2023-07-27 13:19:56 -04:00
Lioncache dcc47074d1 Arm64/Emitter: Simplify SVE Integer Multiply-Add Predicated category 
We can move the op definition into the implementation function.
 2023-07-27 13:16:11 -04:00
Lioncache 4dfee31012 Arm64/Emitter: Simplify SVE FP Recursive Reduction category 
We can move the op constant into the implementation function.
 2023-07-27 13:10:12 -04:00
Lioncache 3749fa6569 Arm64/Emitter: Simplify SVE Float Arithmetic Unpredicated category 
We can move the common assert and op value into the implementation function.
 2023-07-27 13:07:46 -04:00
Mai 94273fbf4f Merge pull request #2760 from Sonicadvance1/switch_to_half_barriers 
Arm64: Switch to using half barriers
 2023-07-27 09:07:14 -04:00