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Author SHA1 Message Date
Lioncache f4d799abdd OpcodeDispatcher: Make use of VDupFromGPR where applicable 
Simplifies some of the IR usage.
 2023-02-13 16:52:51 -05:00
Lioncache 4bb7f49c2a IR: Add VDupFromGPR 
Allows broadcasting constants into vectors from GPRs. Resolves the only
remaining TODOs within our vector ops.
 2023-02-13 16:52:47 -05:00
Ryan Houdek f7f2dc2210 Merge pull request #2403 from lioncash/err 
ARMEmitter/ASIMDOps: Amend a few error logs
 2023-02-13 12:31:52 -08:00
Ryan Houdek d40812929f Merge pull request #2402 from lioncash/shufb 
OpcodeDispatcher: Handle VPSHUFB
 2023-02-13 12:18:16 -08:00
Lioncache c381185a7d ARMEmitter/ASIMDOps: Amend a few error logs 
A few were logging out the wrong instruction name on a precondition
failure.
 2023-02-13 15:17:09 -05:00
Lioncache ac5d09885e OpcodeDispatcher: Handle VPSHUFB 2023-02-13 14:47:37 -05:00
Lioncache d9a505e22e OpcodeDispatcher: Factor PSHUFB implementation into helper 
Will let us centralize the implementation for PSHUFB and VPSHUFB
 2023-02-13 12:39:27 -05:00
Ryan Houdek a96ad0fc9d Merge pull request #2401 from lioncash/palign 
OpcodeDispatcher: Handle VPALIGNR
 2023-02-13 09:35:19 -08:00
Lioncache 9268a356f6 OpcodeDispatcher: Handle VPALIGNR 2023-02-13 10:53:02 -05:00
Lioncache 92141d3edc OpcodeDispatcher: Factor PALIGNR code into helper 
Will allow us to centralize the implementation of PALIGNR and VPALIGNR.
 2023-02-13 09:49:26 -05:00
Ryan Houdek 8c8b680640 Merge pull request #2398 from lioncash/sve2acc 
ARMEmitter: Handle SVE2 Accumulate category
 2023-02-10 23:42:43 -08:00
Lioncache 504be62a92 ARMEmitter: Handle SVE2 integer absolute difference and accumulate 2023-02-11 00:27:07 -05:00
Lioncache 62e2f1b45d ARMEmitter: Handle SVE2 bitwise shift and insert category 2023-02-11 00:27:04 -05:00
Lioncache 880cc72842 ARMEmitter: Handle SVE2 bitwise shift right and accumulate 2023-02-11 00:24:18 -05:00
Lioncache feacd897fc ARMEmitter: Handle SVE2 integer add/sub long with carry category 2023-02-11 00:24:18 -05:00
Lioncache fdd950e1d1 ARMEmitter: Handle SVE2 integer absolute difference and accumulate long category 2023-02-11 00:24:17 -05:00
Lioncache b02af95629 ARMEmitter: Handle SVE2 complex add category 2023-02-10 22:31:45 -05:00
Ryan Houdek 2bd64ad24e Merge pull request #2396 from lioncash/narrow 
ARMEmitter: Finish off SVE Misc category
 2023-02-09 10:28:52 -08:00
Lioncache fa95a823c9 ARMEmitter: Handle SVE2 bitwise shift left long category 2023-02-09 06:30:43 -05:00
Lioncache 399ed61380 ARMEmitter: Handle SVE2 integer add/sub interleaved long 2023-02-09 05:44:44 -05:00
Lioncache 71550e29eb ARMEmitter: Handle SVE integer matrix multiply accumulate 2023-02-09 05:34:11 -05:00
Lioncache 1b8d8f8280 ARMEmitter: Handle SVE2 interleaved XOR category 2023-02-09 05:16:59 -05:00
Lioncache ff6c70f5e1 ARMEmitter: Handle SVE2 bitwise permute category 2023-02-09 05:11:48 -05:00
Lioncache 13ee2b5ec4 ARMEmitter: Handle SVE2 add/sub narrow high part 2023-02-09 05:01:14 -05:00
Ryan Houdek 3c1ba846f7 Merge pull request #2394 from lioncash/cpy 
ARMEmitter: Handle CPY (scalar) and CPY (SIMD&FP, scalar)
 2023-02-09 01:18:17 -08:00
Lioncache 1b4488e7a3 ARMEmitter: Remove outdated histogram TODO 
This was implemented along with histcnt
 2023-02-09 04:04:39 -05:00
Lioncache 6b4df4c998 ARMEmitter: Handle CPY (SIMD&FP, scalar) 2023-02-09 03:53:31 -05:00
Lioncache 2a1ef0ba56 ARMEmitter: Handle CPY (scalar) 2023-02-09 03:46:07 -05:00
Ryan Houdek dd2e70e4aa Merge pull request #2393 from lioncash/wide2 
ARMEmitter: Handle predicated wide shifts
 2023-02-08 23:23:38 -08:00
Lioncache 915a8b23ae ARMEmitter: suffix unpredicated wide shifts 
Keeps the naming convention consistent while avoiding clashing
overloads.
 2023-02-09 02:00:28 -05:00
Lioncache 6eeafd0724 ARMEmitter: Handle predicated wide shifts 2023-02-09 01:58:23 -05:00
Ryan Houdek e6fc159d88 Merge pull request #2390 from lioncash/ext 
OpcodeDispatcher: Handle VEXTRACTF128/VEXTRACTI128
 2023-02-08 22:04:22 -08:00
Ryan Houdek 5fd68b6f07 Merge pull request #2392 from lioncash/wide 
ARMEmitter: Handle unpredicated wide shifts and unpredicated shifts by immediates
 2023-02-08 21:52:23 -08:00
Lioncache 5f80702cf1 ARMEmitter: Handle unpredicated bitwise shift by immediate 2023-02-09 00:15:35 -05:00
Lioncache b45b980b3a ARMEmitter: Handle unpredicated shifts by wide elements 2023-02-09 00:00:17 -05:00
Lioncache f341755e3b Externals: Update fex-gcc-target-test-bins 
Allows filtering out the AVX-enabled tests on non-AVX capable systems.
 2023-02-08 21:54:35 -05:00
Lioncache c53e7d759b guest_test_runner: Handle AVX-only binary tests 
Because the binaries have no metadata, we allow a .json file to be
placed alongside a test indicating required features in a requirements
directory

We also check if the system itself supports those features and run tests
based off of that.
 2023-02-08 21:42:04 -05:00
Mai 143ef57141 Merge pull request #2345 from Sonicadvance1/user_sigreturn 
Support user supplied signal restorer.
 2023-02-08 20:11:47 -05:00
Ryan Houdek 8689038533 Merge pull request #2391 from lioncash/aes 
IR: Allow specifying register size for AES enc/dec ops and PCLMUL
 2023-02-08 17:11:03 -08:00
Lioncache ade34eeda6 gcc tests: Handle pr57275 test 
We now handle all instructions that this uses.
 2023-02-08 17:49:29 -05:00
Lioncache 0218c966bd IR: Allow specifying register size for PCLMUL 
This will allow us to support 256-bit vector operation in the future.
 2023-02-08 16:35:20 -05:00
Lioncache ec5bc9cf3e IR: Allow specifying register sizes for AES enc/dec ops 
This will allow us to support operating on 256-bit vectors.

Currently only sets up the bits and pieces on the x86-64 side, since
facilities for testing the 256-bit operations on ARM isn't set up yet.
 2023-02-08 16:25:19 -05:00
Lioncache 63bf0d5826 OpcodeDispatcher: Handle VEXTRACTI128 2023-02-08 15:46:27 -05:00
Lioncache 2526fa8b6f OpcodeDispatcher: Handle VEXTRACTF128 2023-02-08 15:40:36 -05:00
Mai ef6f5d2003 Merge pull request #2388 from Sonicadvance1/move_fexbash 
FEXBash: Move to Tools folder
 2023-02-07 16:18:55 -05:00
Ryan Houdek be02cafb05 FEXBash: Move to Tools folder 
Just a cleanup, no functional change.
 2023-02-07 07:40:46 -08:00
Ryan Houdek e8fd8ef3b7 Merge pull request #2387 from lioncash/prfx 
Arm64/VectorOps: Use movprfx with VBSL
 2023-02-06 22:53:41 -08:00
Lioncache d7c6ed842d Arm64/VectorOps: Use movprfx with VBSL 
We can use movprfx here to allow compressing the move and bsl operation
together on cpus that can handle it.
 2023-02-07 00:44:08 -05:00
Ryan Houdek 86a6118b62 Merge pull request #2386 from lioncash/bsl 
VectorOps: Only use VBSL 256-bit path if SVE is present
 2023-02-06 21:40:15 -08:00
Lioncache 7a75e43125 VectorOps: Only use VBSL 256-bit path if SVE is present 
With this in place, a _VMov isn't necessary for variable blends anymore,
since the vector upper lanes are guaranteed to be zeroed out in the 128-bit case.
 2023-02-07 00:13:04 -05:00