Stefanos Kornilios Mitsis Poiitidis
07bd2244c7
IR: Remove ShouldInterpret & related logic
2021-02-12 14:21:47 +02:00
Stefanos Kornilios Mitsis Poiitidis
077093eacc
JIT/x64: Use xmm0 as temp instead of xmm11, add xmm11 to RA list
2021-02-12 14:15:22 +02:00
Stefanos Kornilios Mitsis Poiitidis
428111b44b
JIT/arm64: fallback support
2021-02-12 01:23:15 +02:00
Stefanos Kornilios Mitsis Poiitidis
b564927825
IprOps: Add BCDLOAD, BCDSTORE fallbacks
2021-02-11 19:24:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
b0a046dfcb
JIT/IPR: Add fallbacks for almost all x87 ops
2021-02-11 18:52:05 +02:00
Stefanos Kornilios Mitsis Poiitidis
8f5bbde4dd
JIT/x86: Implement VBSL
2021-02-11 18:51:05 +02:00
Stefanos Kornilios Mitsis Poiitidis
7dc0c275cf
Add some basic infrastructure + a few fpr ops
2021-02-11 17:20:29 +02:00
Stefanos Kornilios Mitsis Poiitidis
4e31c1d1ce
RA: Remove erratic assert
2021-02-11 14:31:53 +02:00
Stefanos Kornilios Mitsis Poiitidis
df1c38908c
JIT: Support edge case in CreateElementPair
2021-02-11 14:31:32 +02:00
Stefanos Kornilios Mitsis Poiitidis
fc4b875ff1
Frontend: Only return error if invalid op in first block
2021-02-11 14:31:02 +02:00
Scott Mansell
c4dda4a3f3
arm64: Fix blocks with over 256 spill slots.
...
With multiblock and -n4000, at least one block in geekbench5's camera
benchmark was spilling 324 values. This meant the required stack
adjustment was 5184 bytes, which is larger than can fit into a 12bit
immediate.
Now, it's probally a bug that our RA is spilling that many values, and
we probally should be packing our spill slots closer together, but we
still shouldn't fail to run in this edge case.
So this commit adds a fallback path which uses a temp register to load
the stack adjustment.
2021-02-09 12:08:32 +13:00
Scott Mansell
5b0ade0bd8
Fix power of 2 OP_MUL optimisation
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The new left-shift that replaced the multiply takes
it's size from arg[0]. If arg[0] was 64bit and the original
OP_MUL was 32bit, then the original code would truncate
upper bits, and the replacement code wouldn't.
This bug broke the SSL cert checking code in geekbench,
causing it to fail to upload results.
Fixes #647
2021-02-07 18:49:47 +13:00
Scott Mansell
4fad9a8c0b
Assert on unreachable
2021-02-02 17:12:43 +13:00
Scott Mansell
ef043f10ed
Remove std::unexpected
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It's deprecated in c++17, and android's bionic has removed it
2021-02-01 21:08:45 +13:00
Scott Mansell
93d5cdde1f
Fix missing libc++ includes
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gnu's libc++ is lenient and allows you to miss includes at times.
Android's binoic is more strict and needs these fixes to build.
2021-02-01 21:08:45 +13:00
Scott Mansell
ebb05b56e4
Merge pull request #739 from Sonicadvance1/remove_warnings_10
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Removes warning from Static Register Allocation Pass
2021-02-01 17:31:39 +13:00
Scott Mansell
f5dd0fea5d
Merge pull request #742 from Sonicadvance1/remove_warnings_8
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Removes warning from IRCompaction
2021-02-01 17:31:28 +13:00
Scott Mansell
2e5f59cdc1
Merge pull request #734 from Sonicadvance1/remove_warnings_4
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Removes warnings from OpcodeDispatcher
2021-02-01 16:45:37 +13:00
Scott Mansell
767813eb97
Merge pull request #735 from Sonicadvance1/remove_warnings_5
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Removes warning from X86Tables
2021-02-01 16:44:24 +13:00
Scott Mansell
9c81fbb2fd
Merge pull request #736 from Sonicadvance1/remove_warnings_6
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Removes warning from IRDumper
2021-02-01 16:42:52 +13:00
Scott Mansell
5f624bec05
Merge pull request #733 from Sonicadvance1/remove_warnings_3
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Removes warnings from x86-64 JIT.cpp
2021-02-01 16:42:10 +13:00
Scott Mansell
a156210064
Merge pull request #738 from Sonicadvance1/remove_warnings_9
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Removes warnings from Register Allocation Pass
2021-02-01 16:32:05 +13:00
Scott Mansell
d4fbca3cbf
Merge pull request #732 from Sonicadvance1/remove_warnings_2
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Removes warnings from Frontend
2021-02-01 16:23:29 +13:00
Ryan Houdek
d1161de4e4
Removes warning from Static Register Allocation Pass
2021-01-31 08:00:58 -08:00
Ryan Houdek
0c3ddd3016
Removes warnings from Register Allocation Pass
2021-01-31 08:00:28 -08:00
Ryan Houdek
5c9848650c
Removes warning from IRCompaction
2021-01-31 07:59:59 -08:00
Ryan Houdek
a90e2268f9
Removes warning from DeadStoreElimination
2021-01-31 07:59:26 -08:00
Ryan Houdek
175078b739
Removes warning from IRDumper
2021-01-31 07:58:58 -08:00
Ryan Houdek
9e55f1b177
Removes warning from X86Tables
2021-01-31 07:58:08 -08:00
Ryan Houdek
6012fcfee6
Removes warnings from OpcodeDispatcher
2021-01-31 07:57:28 -08:00
Ryan Houdek
c2f4ea4646
Removes warnings from x86-64 JIT.cpp
2021-01-31 07:56:19 -08:00
Ryan Houdek
1f6017c37c
Removes warnings from Frontend
2021-01-31 07:55:26 -08:00
Stefanos Kornilios Mitsis Poiitidis
1f7d815f3a
LookupCache: Fix crash on L2 insertion
2021-01-29 22:00:07 +02:00
Stefanos Kornilios Mitsis Poiitidis
9ecde7a0b8
Interpreter: Move execution to IntepreterOps::ExecuteIR, single core refactor
2021-01-29 15:17:37 +02:00
Stefanos Kornilios Mitsis Poiitidis
972219043d
Core: Refactor compilation driver, lifetime of objects
2021-01-29 10:42:55 +02:00
Stefanos Kornilios Mitsis Poiitidis
0e00d3dc15
RA: Optimize RAData
2021-01-29 10:42:48 +02:00
Stefanos Kornilios Mitsis Poiitidis
a45c2c34e9
RA: Use RAData directly
2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
513112919b
RA: Move allocation data to RAData
2021-01-29 10:42:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
791aa4c32c
LookupCache: Add a third level cache that will always resolve all known blocks
2021-01-29 01:53:12 +02:00
Stefanos Kornilios Mitsis Poiitidis
0c9e05ed8f
Rename BlockCache to LookupCache
2021-01-29 01:31:48 +02:00
Stefanos Kornilios Mitsis Poiitidis
f872e178ac
Merge pull request #718 from Sonicadvance1/32bit_sigret_handler
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Forces SIGRET handler to the lower 32bits VA on 32bit processes
2021-01-27 20:16:51 +02:00
Stefanos Kornilios Mitsis Poiitidis
ec31dc0872
Merge pull request #716 from Sonicadvance1/describe_tag
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Puts the FEX describe tag in CPUID
2021-01-27 20:10:46 +02:00
Ryan Houdek
2437b89c7b
Forces SIGRET handler to the lower 32bits VA on 32bit processes
...
This is visible to the guest process so for 32bit it needs to be in the
lower 32bits.
2021-01-27 07:54:30 -08:00
Ryan Houdek
5673a0e213
Puts the FEX describe tag in CPUID
...
This is what shows up in /proc/cpuinfo
example on tagged release: 'model name : FEX-2101'
example on untagged release: 'model name : FEX-2101-64-g536be23f'
Fixes #661
2021-01-27 07:20:14 -08:00
Ryan Houdek
3df344a78d
Fixes some asserts from vixl and a bug in ExitSpillSRA
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Assembler by default doesn't allow you to use the assembler. Needs a
CodeBufferCheckScope.
Labels with binds and not links will throw an assert.
ExitSpillSRA was using b instead of bind incorrectly.
Thus branching to a invalid location
2021-01-27 00:53:27 -08:00
Ryan Houdek
6bca290611
Implements VBSL on AArch64
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This isn't quite optimal without RA constraints
2021-01-26 03:01:48 -08:00
Ryan Houdek
513cb27825
Add TSX names to decode tables so we know what they are
...
Rather than just stating UND
We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis
b0365871b6
OpDisp: Address most 32-bit rip size issues
2021-01-25 15:04:12 +02:00
Ryan Houdek
d4ffea5c31
Merge pull request #670 from FEX-Emu/skmp/faster-ra
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IR: Optimize runtime of optimization passes
2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis
0546da7a75
Address review feedback
2021-01-22 11:01:36 +02:00
