Ryan Houdek
513cb27825
Add TSX names to decode tables so we know what they are
...
Rather than just stating UND
We can't support this until we have an ARM CPU that supports TME and
more robust multiblock.
2021-01-26 02:03:42 -08:00
Stefanos Kornilios Mitsis Poiitidis
b0365871b6
OpDisp: Address most 32-bit rip size issues
2021-01-25 15:04:12 +02:00
Ryan Houdek
d4ffea5c31
Merge pull request #670 from FEX-Emu/skmp/faster-ra
...
IR: Optimize runtime of optimization passes
2021-01-22 04:54:08 -08:00
Stefanos Kornilios Mitsis Poiitidis
3bd8731b26
IR: Add CONFIG_VALIDATE_IR_PARSER, enable it on TestHarnessRunner
2021-01-21 21:38:41 +02:00
Stefanos Kornilios Mitsis Poiitidis
13613c6de1
IR: Change ValidateCode to use two uint64_t instead of __uint128_t
2021-01-21 21:37:58 +02:00
Stefanos Kornilios Mitsis Poiitidis
1177c375ff
IR: Further parser cleanups, add fence types
2021-01-21 21:17:27 +02:00
Ryan Houdek
633ea045e5
Handles unaligned cmpxchg/cmpxchg8b in SIGBUS handler
...
cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means
applications rely on unaligned behaviour support with it.
Steam relies on this to work for a linked list array of jobs in some
internal job queueing system. It will end up always aligning by offsets
of 4 since it stores a couple of pointers.
Doesn't currently support the case of unaligned cmpxchg8b crossing a
cacheline, which ends up being semi-broken depending on which x86
behaviour the application is expected.
Intel CPUs do the "Big ring lock" or "split locks". Which means accesses
across cachelines are atomic.
AMD CPUs will tear the value across the cacheline, which is expected x86
behaviour by spec.
If they are expecting Intel behaviour, then that application is just
broken on non-Intel platforms unless they are fine with a tear.
2021-01-20 16:07:50 -08:00
Stefanos Kornilios Mitsis Poiitidis
a9332e604a
JIT/x64: Fix VAddV
2021-01-20 04:26:06 +02:00
Stefanos Kornilios Mitsis Poiitidis
567e315854
Frontend, OpDisp: Don't assert on invalid instructions
2021-01-18 17:19:11 +02:00
Stefanos Kornilios Mitsis Poiitidis
aa0cd76e06
OpDisp: Remove missed debug printf
2021-01-18 10:03:31 +02:00
Ryan Houdek
fbe67db93b
Merge pull request #657 from FEX-Emu/skmp/block-ordering
...
OpDisp: Improved Block Ordering
2021-01-17 23:39:53 -08:00
Ryan Houdek
63f9b62594
Merge pull request #497 from FEX-Emu/skmp/block-linking
...
Block linking
2021-01-17 23:35:40 -08:00
Stefanos Kornilios Mitsis Poiitidis
eb430815ad
Jit: Add Block Linking information
2021-01-16 12:30:32 +02:00
Stefanos Kornilios Mitsis Poiitidis
41d0f84710
OpDisp: Improve block ordering interface, optimize branching order and conds
2021-01-15 21:05:29 +02:00
Stefanos Kornilios Mitsis Poiitidis
5fdbb8a9b2
OpDisp: Improve block ordering for multi-block ops
2021-01-15 21:05:29 +02:00
Ryan Houdek
8d81a925ee
Allows JITSymbols to see central dispatcher
...
Will let us see in perf how much time is spent there
2021-01-14 13:05:24 -08:00
Stefanos Kornilios Mitsis Poiitidis
3507328232
JIT/x64: Add block linking for x86_64
2021-01-13 22:16:07 +02:00
Stefanos Kornilios Mitsis Poiitidis
c46b932b26
JIT/arm64: Implement block linking
2021-01-13 22:03:46 +02:00
Ryan Houdek
e884525434
Fixes 16bit addr offset calculation
...
In the case of 16bit addressing mode, the upper bits 16bits are zext
prior to result.
2021-01-13 12:02:19 -08:00
Ryan Houdek
1084ecf2d3
Fixes more 16bit modrm addressing problems
...
In the case of an instruction that used 16bit addressing mode. It would
calculate the amount of displacement needing to be read using a 32bit
modrm mode. It would then read calculate modrm displacement again and
read the correct number of bytes.
Leftover bytes would then be in a mismatched state which means if an
instruction was using 16bit addressing + modrm + literal at /that/ point
the number of literal bytes remaining would be calculated as a negative.
This didn't actually break things since instructions that have modrm +
literal and can safely use 16bit addressing without breaking in a 32bit
environment is impossible on Linux. Due to the inability to map a memory
range in 16bit range.
2021-01-13 12:02:19 -08:00
Ryan Houdek
96b2c6ca8b
Merge pull request #637 from FEX-Emu/skmp/unsyncronized-rip
...
Dispatch: ExitFunction InlineConstant & unsynchronized rip
2021-01-13 10:58:58 -08:00
Stefanos Kornilios Mitsis Poiitidis
8758348dfd
Dispatch: Support constant Rips, don't syncronize on context on ddisp
2021-01-13 17:26:40 +02:00
duck
ade89bba6a
XXX -> TODO
2021-01-12 15:19:45 -05:00
duck
059594cbd3
Add a quick comment for potential optimization
2021-01-12 15:15:41 -05:00
duck
501bccdd80
Faster PMOVMSKB, part 2
2021-01-12 14:06:52 -05:00
duck
49afb6bceb
Faster PMOVMSKB instruction.
2021-01-12 14:06:51 -05:00
duck
464eb13b93
One-byte horizontal add support on x86-64.
2021-01-12 11:10:16 -05:00
Stefanos Kornilios Mitsis Poiitidis
552895b896
Merge pull request #626 from Sonicadvance1/fix_16bit_addressing
...
Fixes 16bit ModRM rm decoding
2021-01-11 16:19:56 +02:00
duck
a63339c50d
Fix JCC negative offsets as well
2021-01-11 03:34:52 -05:00
duck
e610b12c97
Fix negative offset jumps on x86-32 by using 32-bit RIP
2021-01-11 03:20:25 -05:00
duck
4c295e6dfc
Fix compilation issues, re-rename due to pre-existing variable
2021-01-10 17:54:29 -05:00
duck
3c86a55bea
Size -> GPRSize for a bit more clarity
2021-01-10 17:50:22 -05:00
duck
9290e19fc5
Fix JCXZ on X86
2021-01-10 17:46:03 -05:00
Ryan Houdek
7ee6b68d03
Fixes 16bit ModRM rm decoding
...
When we are running in 32bit mode then it is possible to have an
instruction's modrm working as 16bit mode.
All one needs to do is prefix the instruction with an address size
override
2021-01-10 02:18:30 -08:00
Stefanos Kornilios Mitsis Poiitidis
1dd307f34b
JIT/x64: Implement distributed dispatch, jumps instead of call/ret
2021-01-10 03:23:40 +02:00
Stefanos Kornilios Mitsis Poiitidis
a76baf9a7f
JIT: Fix interpreter fallback path
2021-01-09 05:55:30 +02:00
Stefanos Kornilios Mitsis Poiitidis
f3d5635182
IR: Make ExitFunction take NewRip as an argument, instead of implicit ctx store
2021-01-08 18:41:33 +02:00
Stefanos Kornilios Mitsis Poiitidis
3729a33665
jit: Basic distributed dipatch for arm64
2021-01-08 17:43:18 +02:00
Ryan Houdek
ee8dfb8fc5
Merge pull request #606 from duck-37/sigsegv-fail-tests
...
Have tests that throw a non-HLT SIGSEGV fail
2021-01-06 15:28:38 -08:00
Stefanos Kornilios Mitsis Poiitidis
dd71a45175
Merge branch 'main' into skmp/static-ra
2021-01-07 01:04:16 +02:00
Stefanos Kornilios Mitsis Poiitidis
5600ffbb4b
L1C: Use constant for masking
2021-01-07 00:27:08 +02:00
Stefanos Kornilios Mitsis Poiitidis
aaa80d0678
BlockCache: Add a hash based L1 cache for lookups
2021-01-06 23:37:25 +02:00
duck
f9cd0f0179
Have tests that throw a non-HLT SIGSEGV fail
...
Patch moves HandleSIGSEGV in HostFactory.cpp to a non-frontend host signal handler, then registers its own frontend signal handler to catch unhandled segfaults.
2021-01-06 05:07:47 -05:00
Stefanos Kornilios Mitsis Poiitidis
45b6c39e2c
SRA: reload SRA on signal handler entry, recover from guest on context marshaling
2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
86f74279e6
arm64: Fix SRA spills, OP_SYSCALL stack args
2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
fa35e79c3f
arm64: Fix lr pushing
2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
bcf382afc4
Interpreter: Fix LSHR to correctly zero extend
2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
193a72aa56
SRA: Address review feedback
2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
94fb009f4b
SRA: Address review feedback
2021-01-05 17:14:57 +02:00
Stefanos Kornilios Mitsis Poiitidis
5fd77f8228
arm64: Fix FPR spilling
2021-01-05 17:14:57 +02:00
