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Code Issues Packages Projects Releases 67 Wiki Activity
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2330 Commits
Author SHA1 Message Date
LC 949b205f42 Merge pull request #4462 from Sonicadvance1/passes_initialize_data 
x87StackOptimizationPass: Initialize a couple of arrays
 2025-03-29 18:00:47 -04:00
Ryan Houdek feab0bce4b x87StackOptimizationPass: Initialize a couple of arrays 
Just to silence some warnings that think these aren't zero initialized
before using.
 2025-03-29 14:02:46 -07:00
Ryan Houdek 0599d80b13 FEXCore/Frontend: Changes how VEX operand encoding flags are encoded 
These three options are mutually exclusive with each other and could
potentially result in invalid encodings of the table on accident.

Change over to a 2-bit bitfield to encode if the operand that consumes
the VEX option is none, destination, 1st src, or 2nd src.

This ensures the table can't ever be incorrectly encoded.
 2025-03-29 13:51:02 -07:00
Lioncache 88e6c48db7 X86Tables: Replace deprecated std::is_trivial template 
This is deprecated in C++26, so we can just use a more specific type trait.
 2025-03-29 00:55:15 -04:00
Lioncache bfba74dab9 IR: Replace use of deprecated std::is_trivial_v template 
This is deprecated in C++26
 2025-03-29 00:33:39 -04:00
Ryan Houdek 0ca34d11ad Merge pull request #4454 from alyssarosenzweig/silly-nop 
Fix 66 90 decoding to a nop
 2025-03-28 14:50:02 -07:00
Ryan Houdek bf3275ba4a Merge pull request #4451 from pmatos/SingleStepCheck 
Enable maxinst to 1 only if singlestep exists and is enabled
 2025-03-28 14:45:40 -07:00
Paulo Matos 68b5a90518 Enable maxinst to 1 only if singlestep exists and is enabled 2025-03-28 18:09:52 +01:00
Alyssa Rosenzweig 3a2ca41724 OpcodeDispatcher: handle 66 90 as a NOP 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-28 13:03:34 -04:00
Ryan Houdek d34c287f69 Merge pull request #4450 from lioncash/ilog 
Addressing: Remove unnecessary assert in LoadEffectiveAddress()
 2025-03-28 06:43:31 -07:00
Ryan Houdek b744ca16e1 Merge pull request #4449 from pmatos/ConfigWarnSA 
Remove some warnings from Config.cpp
 2025-03-28 06:43:01 -07:00
Paulo Matos 573c262bb2 Remove some warnings from Config.cpp 
- unused includes, and
- unused functions.
 2025-03-28 14:18:40 +01:00
Lioncache ff2c2f1e1f Addressing: Remove unnecessary assert in LoadEffectiveAddress() 
ilog2 already has an assert for this.
 2025-03-28 06:08:08 -04:00
Lioncache 54dbb9f248 OpcodeDispatcher: Fix potential for uninitialized value use in RCRSmallerOp() 
If Src isn't a constant, then no value is actually assigned to SrcConst, so this
can result in uninitialized arithmetic being performed
 2025-03-28 04:45:40 -04:00
Ryan Houdek 21233430aa Merge pull request #4446 from lioncash/cond 
OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER()
 2025-03-27 20:30:49 -07:00
Ryan Houdek bd1d6820b7 Merge pull request #4438 from Sonicadvance1/static_analysis_wars 
Static analysis warning fixes
 2025-03-27 20:30:37 -07:00
Lioncache 40b1c32008 OpcodeDispatcher: Remove unnecessary 128-bit check in VPGATHER() 
This is already guaranteed to be true, since it's checked in the outer if,
so this can just be a regular else statement.
 2025-03-27 23:08:59 -04:00
Ryan Houdek b5ed804578 Merge pull request #4444 from lioncash/jitcond 
JIT: Simplify SVE 256 operation asserts
 2025-03-27 19:46:23 -07:00
Ryan Houdek fbe3a86c4e Merge pull request #4443 from alyssarosenzweig/ra/cleanup 
RA: small cleanups
 2025-03-27 19:46:14 -07:00
Ryan Houdek ec976f3f75 Merge pull request #4435 from alyssarosenzweig/opt/pall-pf-af 
Pair PF/AF when spilling static regs
 2025-03-27 19:45:29 -07:00
Lioncache 35ee12e7e9 Addressing: Amend binary AND into logical AND in SelectAddressMode() 
Bitwise AND here is a little odd and was likely intended to be a logical AND.
 2025-03-27 17:29:08 -04:00
Lioncache 4497ab8844 JIT: Simplify SVE 256 operation asserts 
We can make these slightly less verbose.
 2025-03-27 16:55:20 -04:00
Alyssa Rosenzweig 9f399f3313 RegisterAllocationPass: rm unused arg to DecodeSRAReg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 16:45:31 -04:00
Alyssa Rosenzweig 3939213336 RegisterAllocationPass: rm useless assertion 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 16:45:31 -04:00
Ryan Houdek b8165813b4 Merge pull request #4439 from pmatos/Init-SA 
Initialize class fields to null/zero
 2025-03-27 09:32:18 -07:00
Alyssa Rosenzweig cb91d585c3 Arm64Emitter: pair pf/af load/store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:07:00 -04:00
Alyssa Rosenzweig 42ea711850 CoreState: squish and rearrange pf_raw/af_raw 
to allow next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 11:04:08 -04:00
Paulo Matos 4565f2b689 Initialize class fields to null/zero 
Silence a couple of static analyzer warnings.
 2025-03-27 15:35:40 +01:00
Alyssa Rosenzweig 2cfc42bd6a Arm64Emitter: simplify and fix !preserve_all regs 
stop doing weird special cases. just dump all the regs except what aapcs64 says
we don't have to.

this fixes saving x18 across thunks and things. so probably fixes things *cry*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-27 10:07:27 -04:00
Ryan Houdek 003de2b659 JIT: static analysis warnings 2025-03-27 04:36:41 -07:00
Ryan Houdek 4ab6c2252d IR: More validation for shifts 2025-03-27 04:36:41 -07:00
Ryan Houdek 8f9d818368 OpcodeDispathcer: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 4ebc307744 IR: Ensure BFE ops can't try to extract element larger than size 2025-03-27 04:26:40 -07:00
Ryan Houdek 0b519b29d9 IR/IRDumper: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 8881e8d96e IR/IREmitter: static analysis warnings 2025-03-27 04:26:40 -07:00
Ryan Houdek 9a99608f68 Passes/ConstProp: static analysis warnings 2025-03-27 04:26:40 -07:00
Alyssa Rosenzweig 7c42c7798c Arm64Emitter: fix a bunch of preserve_all 
* x18 wasn't getting spilled even though it was supposed to be.
* arm64ec preserve_all definitions were all messed up, specialize these to fix.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-26 16:47:39 -04:00
Ryan Houdek ab9123a427 JIT: Fix typo in VSha256U1 2025-03-25 18:19:37 -07:00
Ryan Houdek e504a8c979 Merge pull request #4428 from alyssarosenzweig/opt/vbsl-tie 
Tie VBSL source
 2025-03-25 16:09:17 -07:00
Alyssa Rosenzweig f87edbe1cb JIT: eliminate a zext in bfi 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 17:36:59 -04:00
Alyssa Rosenzweig 694e674fe6 IR: tie VExtr 
needed for sve-256 move reduction.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:22:55 -04:00
Alyssa Rosenzweig 7ebc0f32b8 IR: tie VInsGPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:16:25 -04:00
Alyssa Rosenzweig 68cacc2fc3 IR: tie VFMin/VFMax 
this was missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 15:16:25 -04:00
Alyssa Rosenzweig 43eb597044 IR: tie VBSL source 
this was missed before, noticed while experimenting with round robin RA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2025-03-25 14:14:21 -04:00
Tony Wasserka 7efd827e78 Merge pull request #4378 from bylaws/volmd 
Implement PE volatile metadata support
 2025-03-25 10:23:53 +01:00
Ryan Houdek 2f6f8b93e9 Merge pull request #4424 from Sonicadvance1/converted_options 
Convert config options once
 2025-03-24 19:49:32 -07:00
Ryan Houdek d48413cbec Merge pull request #4426 from alyssarosenzweig/opt/shld-improvements 
Drop some masking in shld
 2025-03-24 19:24:51 -07:00
Billy Laws 51281f6a3a ARM64EC: Load volatile metadata 2025-03-24 22:01:49 +00:00
Billy Laws 7a5e08c5ab FEXCore: Use TSO range information when emitting IR 2025-03-24 22:01:49 +00:00
Billy Laws 642903a7bf FEXCore: Support tracking TSO range information 2025-03-24 22:01:49 +00:00