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Code Issues Packages Projects Releases 67 Wiki Activity
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2735 Commits
Author SHA1 Message Date
LC 22bd10f3b1 CPUBackend: Remove unnecessary reinterpret_casts 
This both take a void*, so the casting is unnecessary to begin with,
since this would occur anyway without it. We can also avoid a
duplication to reduce line noise.
 2026-07-21 08:22:17 -04:00
Ryan Houdek f374b4775a Merge pull request #5769 from lioncash/bound 
Core: Remove unnecessary bounds check in GenerateIR()
 2026-07-18 21:35:34 -07:00
LC ff213bbc5e Core: Move vars closer to usage scope in GenerateIR() 
Makes it so their purpose is more easily seen
 2026-07-21 04:44:47 -04:00
LC 56a4ca6e6a Core: Remove unnecessary bounds check in GenerateIR() 
We already check the bounds in the loop prior to calling at().
 2026-07-21 04:40:22 -04:00
LC 04d06d386f IRDumper: stringstream -> ostringstream 
These are purely output operations, so we don't need to use the more
heavyweight class.
 2026-07-21 04:29:03 -04:00
LC aa26a780ed Merge pull request #5767 from Sonicadvance1/188 
AVX128: Optimize 256-bit vmovmaskpd as well
 2026-07-17 16:56:23 -04:00
Ryan Houdek c4a5ac892f AVX128: Optimize 256-bit vmovmaskpd as well 
Similar to #5757, but once the elements have been zipped together, we
can treat it identically to the 128-bit 32-bit element path.

Closes #3782
 2026-07-17 13:15:47 -07:00
Tony Wasserka c0c95da796 Arm64Emitter: Fix incorrect condition for constant NOP padding 
This needs to be enabled when *generating* caches, not at runtime when we're
loading them (unless we're compiling for validation).

Previous code would incorrectly disable NOP padding in FEXOfflineCompiler and
instead enable it at runtime when it wasn't needed.
 2026-07-17 12:47:51 +02:00
LC c5eddd922d FEXCore: Resolve missing prototype warnings 
Makes sure we mark everything internally linked as necessary, or make
declarations visible to their implementation.
 2026-07-17 02:48:45 -04:00
Ryan Houdek 0467d523c0 Merge pull request #5759 from neobrain/fix_codebuffer_max_size 
CodeCache: Use maximal code buffer size when generating code caches, too
 2026-07-16 13:53:42 -07:00
Ryan Houdek b0af054a95 Merge pull request #5757 from MoonFlowww/avx128-vmovmsk-256 
AVX_128: Optimize VMOVMSKPS from 11 to 7 instructions
 2026-07-16 13:53:00 -07:00
Tony Wasserka 228c351396 CodeCache: Use maximal code buffer size when generating code caches, too 
This is less likely to happen, but will still be required for very large libraries.
 2026-07-16 16:37:18 +02:00
LC 4b4aa1cdbe Arm64Emitter: Pull FillSpecialRegs bools into a struct 
Makes this easily expandable over time without modifying the prototype,
and lets us be a little more informative at call sites.
 2026-07-16 08:07:57 -04:00
moonfloww 3680282b30 new vmovmsk from 11 to 7 ins. 2026-07-16 13:57:12 +02:00
Ryan Houdek 921ce59054 Merge pull request #5750 from lioncash/pred 
VectorOps: Make use of unpredicated shifts
 2026-07-15 09:15:04 -07:00
Ryan Houdek a7627ba39a Merge pull request #5751 from lioncash/sq 
VectorOps: Add trivial case handling in VSQXTN2
 2026-07-15 09:06:59 -07:00
Ryan Houdek 0f2463dda2 Merge pull request #5748 from lioncash/invariant 
RegisterAllocationPass: Ensure pair reg invariant
 2026-07-15 09:04:38 -07:00
LC ba8b0afe7a VectorOps: Use unpredicated shifts where applicable for 256-bit scalar shifts 
Lets us trim some output
 2026-07-15 09:10:57 -04:00
LC 98d45a6a9b VectorOps: Make use of unpredicated immediate shifts 
Same behavior, just without introducing a predicate register dependency.
 2026-07-15 08:00:58 -04:00
LC 6bc808cb06 VectorOps: Add trivial case handling in VSQXTN2 
Lets us generate much more optimal code in the event the destination and
lower source are the same.
 2026-07-15 07:49:50 -04:00
LC d6fb60d512 RegisterAllocationPass: Ensure pair reg invariant 
Allows us to actually catch if this requirement ever gets broken in
the future.
 2026-07-15 06:46:24 -04:00
LC ef35474f88 VectorOps: Simplify 256-bit VAddV 
Didn't read the manual close enough on the first read award.
 2026-07-15 04:43:47 -04:00
LC 9e8e87bbb2 AtomicOps: Avoid constrained unpredictable case in TelemetrySetValue() 
STLXR cannot use the same register as both the status register and the
value register, otherwise it's architecturally unpredictable
behavior.

Only applies to hardware without FEAT_LSE, so this only meaningfully
affects hardware using the v8.0 spec, since FEAT_LSE becomes mandatory
in v8.1 and newer.
 2026-07-13 19:08:17 -04:00
LC 2934b01d58 Vector: Indicate 128-bit zero vector in DefaultX87State() 
Same functional behavior, just makes it visually match the store size
below. Technically also avoids delegating off to the 64-bit element
path if a 128-bit constant zero is already loaded.
 2026-07-13 14:07:12 -04:00
Ryan Houdek 28cdae4687 Merge pull request #5737 from lioncash/bsl 
VectorOps: Simplify SVE 256-bit VOrn with BSL2N
 2026-07-13 10:05:08 -07:00
LC 842e22915c VectorOps: Simplify SVE 256-bit VOrn with BSL2N 
Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.

We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
 2026-07-13 12:27:54 -04:00
LC 24720b67da VectorOps: Make SVE shift==0 case symmetric with ASIMD 
Ensures that we have consistent behavior.
 2026-07-13 10:26:42 -04:00
LC fb2cdc8541 Crypto: Clarify zero vector size in SHA1RNDS4Op() 
This ends up zeroing out the whole 128-bit vector.
 2026-07-12 18:49:27 -04:00
LC 9d3c388664 Crypto: Make use of XAR in SHA1NEXTE when available 
Lets us shave an instruction off on hardware that supports XAR.

Closes #5730
 2026-07-12 16:02:12 -04:00
LC c7f52bcee4 Vector: Centralize masking in InsertScalarFCMPOp 
Ensures that even if someone threw bogus constants in the upper bits of
the immediate, that the special-cased comparison types would still be
handled properly.

We can move the masking in the AVX variant too, just to be consistent.
 2026-07-11 16:07:19 -04:00
LC 929f9a7ad2 Dispatcher: Avoid loading unnecessary reg in vixl single step 
CompileSingleStep only takes one uint64_t, not two.
 2026-07-11 15:03:29 -04:00
Ryan Houdek 821dfe5b98 Merge pull request #5708 from lioncash/mrs 
MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode
 2026-07-11 10:56:27 -07:00
LC 613e9ef701 MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
 2026-07-11 10:24:07 -04:00
LC 5080c6ffc5 MemoryOps: Avoid double application of base offset in {Load,Store}ContextIndexed unaligned case 2026-07-11 09:56:56 -04:00
LC 8b0f07b2dc Syscalls: Remove unnecessary usages of namespace FEXCore::IR 
These aren't necessary.
 2026-07-10 21:02:12 -04:00
Ryan Houdek 650f5b784d Merge pull request #5699 from lioncash/spillops 
Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall
 2026-07-10 10:35:19 -07:00
Ryan Houdek c8dd9eefa6 Merge pull request #5698 from lioncash/dead 
ConversionOps: Remove redundant code in Vector_FToS
 2026-07-10 10:35:06 -07:00
Ryan Houdek 37814111de Merge pull request #5692 from lioncash/unary 
Vector: Use unary handler for scalar unary insertions
 2026-07-10 10:26:44 -07:00
Ryan Houdek 1417888a89 Merge pull request #5691 from lioncash/fpr 
Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp
 2026-07-10 10:25:26 -07:00
LC 8436154276 Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall 
Technically, this parameter wasn't being used at all. It was wired up
for filling, but not spilling.
 2026-07-10 10:10:25 -04:00
LC 150b25f29e ConversionOps: Remove redundant code in Vector_FToS 
These are already defined in an outer scope.
 2026-07-10 09:16:35 -04:00
LC 401e542fcd Vector: Use unary handler for scalar unary insertions 
Same behavior, but just uses a more proper handler.
 2026-07-10 07:27:54 -04:00
LC 210514f74b Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp 2026-07-10 07:24:39 -04:00
LC dd838d4ad3 MemoryOps: Make use of current working reg for cache operations 
TMP1 technically isn't initialized properly here until after the first
iteration.
 2026-07-10 07:13:17 -04:00
Ryan Houdek 5f2d19c7aa Merge pull request #5685 from lioncash/faddv 2026-07-10 03:33:43 -07:00
Ryan Houdek 95e7c866cf Merge pull request #5682 from lioncash/pid 2026-07-10 03:20:23 -07:00
Ryan Houdek 2effdb04bd Merge pull request #5684 from lioncash/midr 2026-07-10 03:18:25 -07:00
LC ede09a03db VectorOps: Fix 256-bit FADDV path 
Avoids falling down to the SVE-128 path.
 2026-07-10 05:50:22 -04:00
LC 849d60253c CPUID: Fix MIDR walking in SetupHostHybridFlag() 2026-07-10 05:46:16 -04:00
LC b5660c8a92 MiscOps: Avoid stack misalignment in ProcessorID 
This needs to be an add.
 2026-07-10 05:41:54 -04:00