Ryan Houdek
d69afaf925
MContext: Insert a stack cookie with assertions enabled
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Pulled from #2176 .
Ensures that when we are handling signals we are actually restoring a
stack state that is what we expect..
While this could randomly intersect with other stack data, it is highly
unlikely and will still capture incorrect stack frames otherwise.
Keeps it out of release build to ensure we aren't sticking random data
in the stack when it wouldn't have even been checked.
2023-01-14 11:59:10 -08:00
CallumDev
806587d6ae
Fix FPREM flags calculation in F64
2023-01-09 22:21:23 +10:30
Ryan Houdek
c2325e1772
Merge pull request #2314 from CallumDev/f64-integer-fix
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F64: Fix integer immediates for add,mul,div,sub
2023-01-08 10:42:21 -08:00
CallumDev
9373fa0c06
F64: Fix integer immediates for add,mul,div,sub
2023-01-09 01:29:17 +10:30
Ryan Houdek
ca9400ba52
Arm64: Fixes large offset spill slots
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Found an application today (hashtree tests) that causes us to spill a
large amount of values on to the stack.
We were encoding larger offsets than what unsigned offset load and store
can handle.
If the offset is too large for the loadstore, use a temporary to put the
offset in to first.
2023-01-07 18:03:24 -08:00
Ryan Houdek
ffd9bb547d
Arm64: Convert ARM Emitter over to new emitter
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Not yet complete. Missing a full SVE implementation and needs
testing/validation.
2023-01-04 05:30:01 -08:00
Ryan Houdek
7a6ef8821f
Arm64: Adds new ARM emitter
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Still needs more work.
Missing operations, cleanup, validation
Notably SVE is missing large chunks.
2023-01-04 05:30:01 -08:00
Ryan Houdek
3904a5264f
Merge pull request #2306 from lioncash/perm
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OpcodeDispatcher: Handle immediate variants of VPERMILPD/VPERMILPS
2022-12-31 21:31:59 -08:00
lioncash
b95c1719c3
OpcodeDispatcher: Handle VPERMILPS (immediate)
2023-01-01 05:15:25 +00:00
lioncash
dfb3f31453
OpcodeDispatcher: Handle VPERMILPD (immediate)
2023-01-01 04:59:48 +00:00
lioncash
8031f76642
OpcodeDispatcher: Handle VMASKMOVDQU
2023-01-01 04:18:46 +00:00
lioncash
ae8a5fa98d
OpcodeDispatcher: Handle VPHSUBD
2023-01-01 03:10:21 +00:00
lioncash
6914598f9a
OpcodeDispatcher: Handle VPHSUBW
2023-01-01 02:42:05 +00:00
lioncash
450aedc8b6
x86_64: Fix 256-bit UnZip/UnZip2
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We weren't swapping the elements so that the operation acts like the two
vectors are concatenated.
2023-01-01 02:42:05 +00:00
lioncash
1e221210a2
OpcodeDispatcher: Move PHSUB impl to helper function
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This will be used for the AVX variants.
2023-01-01 02:42:03 +00:00
Ryan Houdek
58ec2b2d7f
Merge pull request #2303 from lioncash/swizz
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OpcodeDispatcher: Zip elements instead of for loop insertion in PHSUB
2022-12-31 16:09:13 -08:00
lioncash
438adf2f45
x86_64/VectorOps: Handle OpSize==8 case in VUnZip/VUnZip2
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Allows the x86 side of things to execute the new codepath in PHSUB
2022-12-31 23:30:59 +00:00
lioncash
9707e9a4df
OpcodeDispatcher: Zip elements instead of for loop in PHSUB
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Makes this much nicer for 128-bit and soon-to-be 256-bit vectors.
2022-12-31 23:30:38 +00:00
Ryan Houdek
9b8c92e275
Merge pull request #2302 from lioncash/dpp
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OpcodeDispatcher: Handle VDPPD/VDPPS
2022-12-31 15:01:52 -08:00
Ryan Houdek
6caf764b7c
Merge pull request #2301 from lioncash/insps
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OpcodeDispatcher: Handle VINSERTPS
2022-12-31 14:59:11 -08:00
lioncash
769c548ba4
OpcodeDispatcher: Handle VDPPD
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x86 just doesn't have a 256-bit version of this op.
2022-12-31 21:13:20 +00:00
lioncash
dae1676e4a
OpcodeDispatcher: Handle VDPPS
2022-12-31 21:01:48 +00:00
lioncash
74526d1f02
OpcodeDispatcher: Move DPP op impl into helper function
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This will be used to implement the AVX variants.
2022-12-31 21:01:26 +00:00
lioncash
8c005db81c
OpcodeDispatcher: Handle VINSERTPS
2022-12-31 20:23:22 +00:00
lioncash
32b70c8590
OpcodeDispatcher: Move InsertPS impl to helper function
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This will be reused for VINSERTPS
2022-12-31 20:23:18 +00:00
lioncash
bdda14eb75
OpcodeDispatcher: Handle VMOVMSKPD
2022-12-31 19:24:14 +00:00
lioncash
b8c0b0c267
OpcodeDispatcher: Handle VMOVMSKPS
2022-12-31 19:24:11 +00:00
lioncash
ad7dc6ca0a
OpcodeDispatcher: Move ADDSUB table entries
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Makes them numerically ordered.
2022-12-31 19:07:19 +00:00
lioncash
45d7564716
OpcodeDispatcher: Handle VPUNPCKHBW
2022-12-30 14:07:30 +00:00
lioncash
c585bae85d
OpcodeDispatcher: Handle VPUNPCKHWD
2022-12-30 14:01:18 +00:00
lioncash
d07383fa73
OpcodeDispatcher: Handle VPUNPCKHQDQ
2022-12-30 13:54:45 +00:00
lioncash
e1cdcf0651
OpcodeDispatcher: Handle VPUNPCKHDQ
2022-12-30 13:46:53 +00:00
lioncash
ae69aa9a81
OpcodeDispatcher: Handle VUNPCKHPD
2022-12-30 13:18:33 +00:00
lioncash
6341ac6814
OpcodeDispatcher: Handle VUNPCKHPS
2022-12-30 13:05:01 +00:00
lioncash
d91f2ed6b0
OpcodeDispatcher: Handle VPUNPCKLBW
2022-12-29 16:36:45 +00:00
lioncash
7b30a241c0
OpcodeDispatcher: Handle VPUNPCKLWD
2022-12-29 16:30:12 +00:00
lioncash
aaf8e3757d
OpcodeDispatcher: Handle VPUNPCKLQDQ
2022-12-29 16:21:56 +00:00
lioncash
d9c49c4ce1
OpcodeDispatcher: Handle VPUNPCKLDQ
2022-12-29 16:19:09 +00:00
lioncash
9d05c8a67b
OpcodeDispatcher: Handle VUNPCKLPD
2022-12-29 15:12:36 +00:00
lioncash
be9578551a
OpcodeDispatcher: Handle VUNPCKLPS
2022-12-29 15:00:13 +00:00
lioncash
75a01ed2b6
OpcodeDispatcher: Handle VCVTTSD2SI
2022-12-29 10:49:03 +00:00
lioncash
3ebe141032
OpcodeDispatcher: Handle VCVTSD2SI
2022-12-29 10:43:10 +00:00
lioncash
31e332bd61
OpcodeDispatcher: Handle VCVTTSS2SI
2022-12-29 10:26:19 +00:00
lioncash
764324d557
OpcodeDispatcher: Handle VCVTSS2SI
2022-12-29 10:16:12 +00:00
lioncash
2a7795fe2c
OpcodeDispatcher: Handle VCVTTPD2DQ
2022-12-28 12:01:53 +00:00
lioncash
b00b41b8fa
OpcodeDispatcher: Handle VCVTPD2DQ
2022-12-28 11:54:28 +00:00
lioncash
39396789b1
Interpreter/ConversionOps: Prevent out of bounds/excessive element handling in Vector_FToF
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Previously this could access more elements than it needs to.
In the case where we pass in a 128-bit vector and perform a 128-bit
operation, only two doubles should be handled, but in this case will
actually try and handle four double elements.
Consider converting doubles within a vector into floats:
e.g. _Vector_FToF(16, 4, Src, 8)
16 is our OpSize
4 is our DestElementSize
Src is our input vector
8 is the SrcElementSize
(OpSize << 1) / Op->SrcElementSize becomes:
(16 << 1) / 8 ->
32 / 8 ->
4
What we actually want it 2 here, we're indexing 128-bit vectors out of
its bounds (not a problem now, since we assume up to 256-bit in the
interpreter).
Similarly with 256-bit vectors
_Vector_FToF(32, 4, Src, 8)
would become:
64 / 8 -> 8
where we actually want 4, since we only have 4 64-bit elements in a
256-bit vector.
This corrects this in the interpreter by just special-casing the 64-bit
calculation.
2022-12-28 11:53:29 +00:00
lioncash
38a2886a59
OpcodeDispatcher: Handle VCVTTPS2DQ
2022-12-28 07:54:16 +00:00
lioncash
bd8e1a80f6
OpcodeDispatcher: Handle VCVTPS2DQ
2022-12-28 07:45:37 +00:00
lioncash
dfa113dcdb
OpcodeDispatcher: Move Vector_CVT_Float_To_Int to helper function
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This can be reused for the AVX variant.
2022-12-23 17:33:15 +00:00
Ryan Houdek