Alyssa Rosenzweig 18783948f7 OpcodeDispatcher: Optimize non-immediate shift ...

Similar to the immediate case, but now we select between the entire old
and new NZCV registers. This is faster than selecting each bit
independently. Saves 11 instructions for calculating flags for "shl eax,
cl".

2023-08-02 14:45:10 -04:00

..

Config

FEXCore: Remove erroneous asserts in the project

2023-07-28 13:36:05 -07:00

Context

Context: Make BackendFeatures public

2023-08-02 12:38:00 -04:00

Core

OpcodeDispatcher: Optimize non-immediate shift

2023-08-02 14:45:10 -04:00

GDBJIT

SourcecodeResolver: Convert string to fextl

2023-03-16 03:21:45 -07:00

HLE/Thunks

Thunks: Mostly reverts #2672

2023-05-18 15:50:55 -07:00

IR

IR: Add TEST opcode

2023-08-02 12:38:00 -04:00