Alyssa Rosenzweig 196a0531e0 OpcodeDispatcher: optimize nzcv with asimd masked load/store ...

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-06-27 10:37:06 -04:00

..

Config

HostFeatures: Removes distinction between AVX and AVX2

2024-06-26 14:56:01 -07:00

Context

FEXCore: Implement support for fetching/setting YMM registers

2024-06-21 17:13:56 -04:00

Core

OpcodeDispatcher: optimize nzcv with asimd masked load/store

2024-06-27 10:37:06 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

IR: specify registers, not offsets for SRA

2024-05-08 14:01:42 -04:00

IR

IR: Split Vector_FToF2 in to VFCVTL2 and VCVTFN2

2024-06-26 14:03:41 -07:00