Files
FEX-Emu--FEX/External/FEXCore/Source/Interface/Core
Ryan Houdek 1fecf89bfc Arm64: Inline Syscall spill optimization
This was likely an issue with signals racing to the spill handler, which
we have fixed bugs with over the past few months.

This means we don't need to spill all SRA GPR registers anymore, at most
we need to spill three registers that intersect with syscall arguments.
2022-12-16 10:04:16 -08:00
..
2020-03-06 09:07:37 +02:00
2022-03-22 16:53:44 -07:00
2020-03-06 09:07:37 +02:00
2022-03-13 13:05:00 -07:00
2021-08-28 00:32:15 -07:00