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Alyssa Rosenzweig
65ee1fafa8
This sideband is now unused, registers are encoded directly in the IR. So we can garbage collect all this code for quite some savings. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
32 lines
898 B
C++
32 lines
898 B
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include <FEXCore/fextl/memory.h>
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namespace FEXCore {
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class CPUIDEmu;
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struct HostFeatures;
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} // namespace FEXCore
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namespace FEXCore::Utils {
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class IntrusivePooledAllocator;
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}
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namespace FEXCore::IR {
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class Pass;
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class RegisterAllocationPass;
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fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool SupportsTSOImm9, const FEXCore::CPUIDEmu* CPUID);
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fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
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fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass();
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fextl::unique_ptr<FEXCore::IR::Pass> CreateX87StackOptimizationPass(const FEXCore::HostFeatures&, OpSize GPROpSize);
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namespace Validation {
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fextl::unique_ptr<FEXCore::IR::Pass> CreateIRValidation();
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} // namespace Validation
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namespace Debug {
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fextl::unique_ptr<FEXCore::IR::Pass> CreateIRDumper();
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}
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} // namespace FEXCore::IR
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