Alyssa Rosenzweig 42b5b1f64c Core: partially flush register cache per instruction ...

This will mitigate problems later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-07-10 11:36:18 -04:00

..

Config

HostFeatures: Removes distinction between AVX and AVX2

2024-06-26 14:56:01 -07:00

Context

FEXCore: Implement support for fetching/setting YMM registers

2024-06-21 17:13:56 -04:00

Core

Core: partially flush register cache per instruction

2024-07-10 11:36:18 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

IR: specify registers, not offsets for SRA

2024-05-08 14:01:42 -04:00

IR

Merge pull request #3842 from Sonicadvance1/fix_f64_to_i32

2024-07-09 03:49:31 -04:00