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Ryan Houdek
2d800b2627
These address calculations were failing to understand that they can be optimized. When TSO emulation is disabled these were fine, but with TSO we were eating one more instruction. Before: ``` add x20, x12, #0x4 (4) dmb ish ldr s16, [x20] dmb ish ``` After: ``` dmb ish ldr s16, [x12, #4] dmb ish ``` Also left a note that once LRCPC3 is supported in hardware that we can do a similar optimization there.