mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-24 18:00:44 +02:00
Ryan Houdek
da263834f8
Spurred on by #3421 This does a bunch of GPR and vector loads to showcase addressing limitations between ARM and x86. Tests: - 8/16/32/64-bit GPR loads - Both 32-bit and 64-bit addressing modes - 32/64/128-bit Vector loads - Both 32-bit and 64-bit addressing modes - Duplicate the tests for 32-bit addressing mode with a 32-bit process - Since it should change behaviour. Untested: - 8/16-bit vector loadstores since those don't exist on x86 - 16-bit x87 integer load exists but that doesn't go through a vector load in FEX.
346 lines
8.3 KiB
JSON
346 lines
8.3 KiB
JSON
{
|
|
"Features": {
|
|
"Bitness": 32,
|
|
"EnabledHostFeatures": [],
|
|
"DisabledHostFeatures": [
|
|
"SVE128",
|
|
"SVE256",
|
|
"RPRES",
|
|
"AFP"
|
|
]
|
|
},
|
|
"Comment": [
|
|
"Instructions that explicitly push against the limits of ARM's loadstore instructions"
|
|
],
|
|
"Instructions": {
|
|
"movzx eax, byte [ecx - 257]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfffffeff",
|
|
"add w20, w5, w20",
|
|
"ldrb w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, byte [ecx - 256]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"add w20, w5, w20",
|
|
"ldrb w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, byte [ecx + 255]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xff (255)",
|
|
"ldrb w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, byte [ecx + 256]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x100 (256)",
|
|
"ldrb w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, byte [ecx + 4095]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xfff (4095)",
|
|
"ldrb w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, byte [ecx + 4096]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x1000 (4096)",
|
|
"ldrb w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx - 257]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfffffeff",
|
|
"add w20, w5, w20",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx - 256]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"add w20, w5, w20",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx + 255]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xff (255)",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx + 256]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x100 (256)",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx + 8190]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1ffe",
|
|
"add w20, w5, w20",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx + 8191]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1fff",
|
|
"add w20, w5, w20",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"movzx eax, word [ecx + 8192]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x2000 (8192)",
|
|
"ldrh w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx - 257]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfffffeff",
|
|
"add w20, w5, w20",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx - 256]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"add w20, w5, w20",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 255]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xff (255)",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 256]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x100 (256)",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 16380]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffc",
|
|
"add w20, w5, w20",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 16381]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffd",
|
|
"add w20, w5, w20",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 16382]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffe",
|
|
"add w20, w5, w20",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 16383]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3fff",
|
|
"add w20, w5, w20",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"mov eax, dword [ecx + 16384]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x4000 (16384)",
|
|
"ldr w4, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx + 16379]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffb",
|
|
"add w20, w5, w20",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx + 16380]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffc",
|
|
"add w20, w5, w20",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx + 16381]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3ffd",
|
|
"add w20, w5, w20",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx - 257]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfffffeff",
|
|
"add w20, w5, w20",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx - 256]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"add w20, w5, w20",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx + 255]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xff (255)",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movss xmm0, [ecx + 256]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x100 (256)",
|
|
"ldr s16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx + 32759]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x7ff7",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx + 32760]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x7ff8",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx + 32761]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x7ff9",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx - 257]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfffffeff",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx - 256]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx + 255]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xff (255)",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movsd xmm0, [ecx + 256]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x100 (256)",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx + 65519]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffef",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx + 65520]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfff0",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx + 65521]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfff1",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx - 257]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xfffffeff",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx - 256]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"add w20, w5, w20",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx + 255]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0xff (255)",
|
|
"ldr d16, [x20]"
|
|
]
|
|
},
|
|
"movq xmm0, [ecx + 256]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"add w20, w5, #0x100 (256)",
|
|
"ldr d16, [x20]"
|
|
]
|
|
}
|
|
}
|
|
}
|