mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-27 14:00:53 +01:00
3241 lines
83 KiB
JSON
3241 lines
83 KiB
JSON
{
|
|
"Features": {
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"Bitness": 64,
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|
"EnabledHostFeatures": [],
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|
"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FLAGM",
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|
"FLAGM2"
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]
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|
},
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|
"Comment": [
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|
"Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
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|
"Flags calculation can dramatically change an instruction's lengths so this is mostly ignored here."
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|
],
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"Instructions": {
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|
"add al, 1": {
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|
"ExpectedInstructionCount": 7,
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|
"Comment": "GROUP1 0x80 /0",
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|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
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|
"mov x27, x4",
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|
"lsl w0, w27, #24",
|
|
"cmn w0, w20, lsl #24",
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|
"add w26, w27, #0x1 (1)",
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|
"mov x4, x27",
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|
"bfxil x4, x26, #0, #8"
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|
]
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|
},
|
|
"or al, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x80 /1",
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|
"ExpectedArm64ASM": [
|
|
"orr w26, w4, #0x1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
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|
]
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|
},
|
|
"adc al, 1": {
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|
"ExpectedInstructionCount": 20,
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|
"Comment": "GROUP1 0x80 /2",
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|
"ExpectedArm64ASM": [
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|
"mov w20, #0x1",
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|
"mov x27, x4",
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|
"cset w21, hs",
|
|
"adc w20, w27, w20",
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|
"uxtb w26, w20",
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|
"cmp w26, #0x1 (1)",
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|
"cset x20, lo",
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|
"cmp w26, #0x1 (1)",
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|
"cset x22, ls",
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|
"cmp x21, #0x1 (1)",
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|
"csel x20, x22, x20, eq",
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|
"cmn wzr, w26, lsl #24",
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|
"mrs x21, nzcv",
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|
"orr w20, w21, w20, lsl #29",
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|
"bic w21, w26, w27",
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|
"ubfx x21, x21, #7, #1",
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|
"orr w20, w20, w21, lsl #28",
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|
"mov x4, x27",
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"bfxil x4, x26, #0, #8",
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"msr nzcv, x20"
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]
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},
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|
"sbb al, 1": {
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|
"ExpectedInstructionCount": 21,
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|
"Comment": "GROUP1 0x80 /3",
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|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
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|
"mov x27, x4",
|
|
"cset w21, hs",
|
|
"add w20, w20, w21",
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|
"sub w20, w27, w20",
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|
"uxtb w26, w20",
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|
"cmp x26, x27",
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|
"cset x20, hi",
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|
"cmp x26, x27",
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|
"cset x22, hs",
|
|
"cmp x21, #0x1 (1)",
|
|
"csel x20, x22, x20, eq",
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|
"cmn wzr, w26, lsl #24",
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|
"mrs x21, nzcv",
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|
"orr w20, w21, w20, lsl #29",
|
|
"bic w21, w27, w26",
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|
"ubfx x21, x21, #7, #1",
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|
"orr w20, w20, w21, lsl #28",
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|
"mov x4, x27",
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|
"bfxil x4, x26, #0, #8",
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"msr nzcv, x20"
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|
]
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|
},
|
|
"and al, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x80 /4",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0x1",
|
|
"cmn wzr, w26, lsl #24",
|
|
"bfxil x4, x26, #0, #8"
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|
]
|
|
},
|
|
"sub al, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x80 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w27, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
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|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x27",
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|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
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|
]
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|
},
|
|
"xor al, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x80 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w4, #0x1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
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|
]
|
|
},
|
|
"cmp al, 1": {
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|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP1 0x80 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w27, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"add al, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x80 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"eor w27, w4, #0xff",
|
|
"lsl w0, w4, #24",
|
|
"cmn w0, w20, lsl #24",
|
|
"add w26, w4, #0xff (255)",
|
|
"bfxil x4, x26, #0, #8"
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|
]
|
|
},
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|
"or al, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x80 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr w26, w4, #0xff",
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|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
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|
]
|
|
},
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|
"adc al, -1": {
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|
"ExpectedInstructionCount": 19,
|
|
"Comment": "GROUP1 0x80 /2",
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|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"eor w27, w4, #0xff",
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|
"cset w21, hs",
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|
"adc w20, w4, w20",
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|
"uxtb w26, w20",
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|
"cmp w26, #0xff (255)",
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"cset x20, lo",
|
|
"cmp w26, #0xff (255)",
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|
"cset x22, ls",
|
|
"cmp x21, #0x1 (1)",
|
|
"csel x20, x22, x20, eq",
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|
"cmn wzr, w26, lsl #24",
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|
"mrs x21, nzcv",
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|
"orr w20, w21, w20, lsl #29",
|
|
"bic w21, w4, w26",
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"ubfx x21, x21, #7, #1",
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"orr w20, w20, w21, lsl #28",
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|
"bfxil x4, x26, #0, #8",
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|
"msr nzcv, x20"
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|
]
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|
},
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|
"sbb al, -1": {
|
|
"ExpectedInstructionCount": 20,
|
|
"Comment": "GROUP1 0x80 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"eor w27, w4, #0xff",
|
|
"cset w21, hs",
|
|
"add w20, w20, w21",
|
|
"sub w20, w4, w20",
|
|
"uxtb w26, w20",
|
|
"cmp x26, x4",
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|
"cset x20, hi",
|
|
"cmp x26, x4",
|
|
"cset x22, hs",
|
|
"cmp x21, #0x1 (1)",
|
|
"csel x20, x22, x20, eq",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"bic w21, w26, w4",
|
|
"ubfx x21, x21, #7, #1",
|
|
"orr w20, w20, w21, lsl #28",
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|
"bfxil x4, x26, #0, #8",
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|
"msr nzcv, x20"
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|
]
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|
},
|
|
"and al, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x80 /4",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w4, #0xff",
|
|
"cmn wzr, w26, lsl #24",
|
|
"bfxil x4, x26, #0, #8"
|
|
]
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|
},
|
|
"sub al, -1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP1 0x80 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"eor w27, w4, #0xff",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, #0xff (255)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor al, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x80 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor w26, w4, #0xff",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"cmp al, -1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP1 0x80 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"eor w27, w4, #0xff",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w4, #0xff (255)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"add ax, 256": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x81 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x100",
|
|
"mov x27, x4",
|
|
"lsl w0, w27, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w27, #0x100 (256)",
|
|
"mov x4, x27",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"add eax, 256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"adds w26, w27, #0x100 (256)",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"add rax, 256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"adds x26, x27, #0x100 (256)",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"or eax, 256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr w4, w4, #0x100",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"or rax, 256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr x4, x4, #0x100",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"adc eax, 256": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x81 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x100",
|
|
"mov x27, x4",
|
|
"adcs w26, w27, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc rax, 256": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x81 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x100",
|
|
"mov x27, x4",
|
|
"adcs x26, x27, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sbb eax, 256": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x81 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x100",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs w26, w27, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rax, 256": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x81 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x100",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs x26, x27, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"and eax, 256": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP1 0x81 /4",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, #0x100",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and rax, 256": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP1 0x81 /4",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, #0x100",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sub eax, 256": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x81 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs w26, w27, #0x100 (256)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rax, 256": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x81 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs x26, x27, #0x100 (256)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor eax, 256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor w4, w4, #0x100",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"xor rax, 256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor x4, x4, #0x100",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"cmp eax, 256": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "GROUP1 0x81 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs w26, w27, #0x100 (256)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rax, 256": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "GROUP1 0x81 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs x26, x27, #0x100 (256)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"add ax, -256": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x81 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff00",
|
|
"mov x27, x4",
|
|
"lsl w0, w27, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w27, w20",
|
|
"mov x4, x27",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"add eax, -256": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x81 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"mov x27, x4",
|
|
"adds w26, w27, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"add rax, -256": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x81 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffff00",
|
|
"mov x27, x4",
|
|
"adds x26, x27, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"or eax, -256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr w4, w4, #0xffffff00",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"or rax, -256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr x4, x4, #0xffffffffffffff00",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"adc eax, -256": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x81 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"mov x27, x4",
|
|
"adcs w26, w27, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc rax, -256": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x81 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffff00",
|
|
"mov x27, x4",
|
|
"adcs x26, x27, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sbb eax, -256": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x81 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs w26, w27, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rax, -256": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x81 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffff00",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs x26, x27, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"and eax, -256": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP1 0x81 /4",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, #0xffffff00",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and rax, -256": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP1 0x81 /4",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, #0xffffffffffffff00",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sub eax, -256": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x81 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"mov x27, x4",
|
|
"subs w26, w27, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rax, -256": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x81 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffff00",
|
|
"mov x27, x4",
|
|
"subs x26, x27, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor eax, -256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor w4, w4, #0xffffff00",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"xor rax, -256": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x81 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor x4, x4, #0xffffffffffffff00",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"cmp eax, -256": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x81 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffff00",
|
|
"mov x27, x4",
|
|
"subs w26, w27, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rax, -256": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x81 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffff00",
|
|
"mov x27, x4",
|
|
"subs x26, x27, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"add ax, 1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x83 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"lsl w0, w27, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w27, #0x1 (1)",
|
|
"mov x4, x27",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"add eax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"adds w26, w27, #0x1 (1)",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"add rax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"adds x26, x27, #0x1 (1)",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"or eax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr w4, w4, #0x1",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"or rax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /1",
|
|
"ExpectedArm64ASM": [
|
|
"orr x4, x4, #0x1",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"adc eax, 1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"adcs w26, w27, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc rax, 1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"adcs x26, x27, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sbb eax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x83 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs w26, w27, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x83 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"mov x27, x4",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs x26, x27, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"and eax, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP1 0x83 /4",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w4, #0x1",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and rax, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP1 0x83 /4",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x4, #0x1",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sub eax, 1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x83 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rax, 1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x83 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs x26, x27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor eax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor w4, w4, #0x1",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"xor rax, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /6",
|
|
"ExpectedArm64ASM": [
|
|
"eor x4, x4, #0x1",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"cmp eax, 1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "GROUP1 0x83 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rax, 1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "GROUP1 0x83 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"subs x26, x27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"add ax, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x83 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffff",
|
|
"eor w27, w4, #0xffff",
|
|
"lsl w0, w4, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w4, w20",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"add eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w27, w4, w20",
|
|
"adds w26, w4, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"add rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor w27, w4, w20",
|
|
"adds x26, x4, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"or eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /-1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"orr w4, w4, w20",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"or rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /-1",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"orr x4, x4, x20",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"adc eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w27, w4, w20",
|
|
"adcs w26, w4, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"adc rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor w27, w4, w20",
|
|
"adcs x26, x4, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sbb eax, -1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x83 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w27, w4, w20",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sbb rax, -1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP1 0x83 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor w27, w4, w20",
|
|
"mrs x21, nzcv",
|
|
"eor w21, w21, #0x20000000",
|
|
"msr nzcv, x21",
|
|
"sbcs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"and eax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"ands w26, w4, w20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"and rax, -1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "GROUP1 0x83 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"ands x26, x4, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"sub eax, -1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x83 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sub rax, -1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP1 0x83 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"xor eax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /6",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w4, w4, w20",
|
|
"mov x26, x4",
|
|
"tst w4, w4"
|
|
]
|
|
},
|
|
"xor rax, -1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "GROUP1 0x83 /6",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor x4, x4, x20",
|
|
"mov x26, x4",
|
|
"tst x4, x4"
|
|
]
|
|
},
|
|
"cmp eax, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x83 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"eor w27, w4, w20",
|
|
"subs w26, w4, w20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"cmp rax, -1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP1 0x83 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"eor w27, w4, w20",
|
|
"subs x26, x4, x20",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol al, 2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xC0 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"bfi w20, w4, #8, #8",
|
|
"bfi w20, w20, #16, #16",
|
|
"ror w20, w20, #30",
|
|
"bfxil x4, x20, #0, #8",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror al, 2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xC0 /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"bfi w20, w4, #8, #8",
|
|
"ror w20, w20, #2",
|
|
"bfxil x4, x20, #0, #8",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl al, 2": {
|
|
"ExpectedInstructionCount": 20,
|
|
"Comment": "GROUP2 0xC0 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"cset w21, hs",
|
|
"uxtb w22, w4",
|
|
"bfi x20, x22, #55, #8",
|
|
"bfi x20, x21, #63, #1",
|
|
"bfi x20, x22, #46, #8",
|
|
"bfi x20, x21, #54, #1",
|
|
"bfi x20, x22, #37, #8",
|
|
"bfi x20, x21, #45, #1",
|
|
"bfi x20, x22, #28, #8",
|
|
"bfi x20, x21, #36, #1",
|
|
"bfi x20, x22, #19, #8",
|
|
"bfi x20, x21, #27, #1",
|
|
"bfxil x20, x22, #0, #8",
|
|
"ror x21, x20, #62",
|
|
"bfxil x4, x21, #0, #8",
|
|
"ror x20, x20, #61",
|
|
"ubfx x20, x20, #0, #1",
|
|
"lsl x20, x20, #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr al, 2": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xC0 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"uxtb w21, w4",
|
|
"mov x0, x21",
|
|
"bfi x0, x20, #8, #1",
|
|
"mov x20, x0",
|
|
"bfi x20, x20, #9, #9",
|
|
"bfi x20, x20, #18, #18",
|
|
"bfi x20, x20, #36, #9",
|
|
"lsr x21, x20, #2",
|
|
"bfxil x4, x21, #0, #8",
|
|
"ubfx x20, x20, #1, #1",
|
|
"lsl x20, x20, #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl al, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC0 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"lsl w26, w20, #2",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #6, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr al, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC0 /5",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"lsr w26, w20, #2",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar al, 2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xC0 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"sxtb x20, w20",
|
|
"asr x26, x20, #2",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol ax, 2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xC1 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"bfi w20, w4, #16, #16",
|
|
"ror w20, w20, #30",
|
|
"bfxil x4, x20, #0, #16",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol eax, 2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP2 0xC1 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ror w4, w4, #30",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x21, x4, #0, #1",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol rax, 2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP2 0xC1 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ror x4, x4, #62",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x21, x4, #0, #1",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror ax, 2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xC1 /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"bfi w20, w4, #16, #16",
|
|
"ror w20, w20, #2",
|
|
"bfxil x4, x20, #0, #16",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror eax, 2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP2 0xC1 /1",
|
|
"ExpectedArm64ASM": [
|
|
"ror w4, w4, #2",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x21, x4, #31, #1",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror rax, 2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP2 0xC1 /1",
|
|
"ExpectedArm64ASM": [
|
|
"ror x4, x4, #2",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"lsr x21, x4, #63",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl ax, 2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xC1 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"cset w21, hs",
|
|
"uxth w22, w4",
|
|
"bfi x20, x22, #47, #16",
|
|
"bfi x20, x21, #63, #1",
|
|
"bfi x20, x22, #30, #16",
|
|
"bfi x20, x21, #46, #1",
|
|
"bfi x20, x22, #13, #16",
|
|
"bfi x20, x21, #29, #1",
|
|
"bfxil x20, x22, #0, #16",
|
|
"ror x21, x20, #62",
|
|
"bfxil x4, x21, #0, #16",
|
|
"ror x20, x20, #61",
|
|
"ubfx x20, x20, #0, #1",
|
|
"lsl x20, x20, #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl eax, 2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xC1 /2",
|
|
"ExpectedArm64ASM": [
|
|
"lsl w20, w4, #2",
|
|
"cset w21, hs",
|
|
"orr w20, w20, w4, lsr #31",
|
|
"ubfx x22, x4, #30, #1",
|
|
"lsl x22, x22, #29",
|
|
"orr w4, w20, w21, lsl #1",
|
|
"msr nzcv, x22"
|
|
]
|
|
},
|
|
"rcl rax, 2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xC1 /2",
|
|
"ExpectedArm64ASM": [
|
|
"lsl x20, x4, #2",
|
|
"cset w21, hs",
|
|
"orr x20, x20, x4, lsr #63",
|
|
"ubfx x22, x4, #62, #1",
|
|
"lsl x22, x22, #29",
|
|
"orr x4, x20, x21, lsl #1",
|
|
"msr nzcv, x22"
|
|
]
|
|
},
|
|
"rcr ax, 2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xC1 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"uxth w21, w4",
|
|
"mov x0, x21",
|
|
"bfi x0, x20, #16, #1",
|
|
"mov x20, x0",
|
|
"bfi x20, x20, #17, #17",
|
|
"bfi x20, x20, #34, #17",
|
|
"lsr x21, x20, #2",
|
|
"bfxil x4, x21, #0, #16",
|
|
"ubfx x20, x20, #1, #1",
|
|
"lsl x20, x20, #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr eax, 2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xC1 /3",
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w4, #2",
|
|
"cset w21, hs",
|
|
"orr w20, w20, w4, lsl #31",
|
|
"ubfx x22, x4, #1, #1",
|
|
"lsl x22, x22, #29",
|
|
"orr w4, w20, w21, lsl #30",
|
|
"msr nzcv, x22"
|
|
]
|
|
},
|
|
"rcr rax, 2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xC1 /3",
|
|
"ExpectedArm64ASM": [
|
|
"lsr x20, x4, #2",
|
|
"cset w21, hs",
|
|
"orr x20, x20, x4, lsl #63",
|
|
"ubfx x22, x4, #1, #1",
|
|
"lsl x22, x22, #29",
|
|
"orr x4, x20, x21, lsl #62",
|
|
"msr nzcv, x22"
|
|
]
|
|
},
|
|
"shl ax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"lsl w26, w20, #2",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #14, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl eax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"lsl w4, w20, #2",
|
|
"tst w4, w4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #30, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl rax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsl x4, x20, #2",
|
|
"tst x4, x4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #62, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr ax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /5",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"lsr w26, w20, #2",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr eax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"lsr w4, w20, #2",
|
|
"tst w4, w4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr rax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsr x4, x20, #2",
|
|
"tst x4, x4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar ax, 2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xC1 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"sxth x20, w20",
|
|
"asr x26, x20, #2",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar eax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"asr w4, w20, #2",
|
|
"tst w4, w4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar rax, 2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xC1 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"asr x4, x20, #2",
|
|
"tst x4, x4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #1, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol al, 1": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xd0 /0",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"bfi w20, w20, #8, #8",
|
|
"bfi w20, w20, #16, #16",
|
|
"ror w20, w20, #31",
|
|
"bfxil x4, x20, #0, #8",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #7",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror al, 1": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xd0 /1",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"bfi w20, w20, #8, #8",
|
|
"ror w20, w20, #1",
|
|
"bfxil x4, x20, #0, #8",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #7, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #1",
|
|
"ubfx x20, x20, #6, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl al, 1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": "GROUP2 0xd0 /2",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"cset w21, hs",
|
|
"orr w21, w21, w20, lsl #1",
|
|
"bfxil x4, x21, #0, #8",
|
|
"ubfx x22, x20, #7, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w22, #29, #1",
|
|
"mov w22, w0",
|
|
"eor w20, w21, w20",
|
|
"ubfx x20, x20, #7, #1",
|
|
"mov w0, w22",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr al, 1": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd0 /3",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"cset w21, hs",
|
|
"ubfx x22, x20, #0, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w22, #29, #1",
|
|
"mov w22, w0",
|
|
"ubfx w20, w20, #1, #7",
|
|
"bfi w20, w21, #7, #1",
|
|
"bfxil x4, x20, #0, #8",
|
|
"eor w20, w20, w20, lsr #1",
|
|
"ubfx x20, x20, #6, #1",
|
|
"mov w0, w22",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl al, 1": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xd0 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"lsl w21, w20, #1",
|
|
"bfxil x4, x21, #0, #8",
|
|
"uxtb w26, w21",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #7, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w26, w20",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr al, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xd0 /5",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"lsr w26, w20, #1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar al, 1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xd0 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"sxtb x20, w20",
|
|
"asr w26, w20, #1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cmn wzr, w26, lsl #24",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol ax, 1": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xd1 /0",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"bfi w20, w20, #16, #16",
|
|
"ror w20, w20, #31",
|
|
"bfxil x4, x20, #0, #16",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #15",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol eax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xd1 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"ror w4, w20, #31",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x21, x4, #0, #1",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"eor w21, w4, w4, lsr #31",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol rax, 1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xd1 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ror x4, x4, #63",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x21, x4, #0, #1",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"eor x21, x4, x4, lsr #63",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror ax, 1": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xd1 /1",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"bfi w20, w20, #16, #16",
|
|
"ror w20, w20, #1",
|
|
"bfxil x4, x20, #0, #16",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #15, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #1",
|
|
"ubfx x20, x20, #14, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror eax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xd1 /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"ror w4, w20, #1",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x21, x4, #31, #1",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"eor w21, w4, w4, lsr #1",
|
|
"ubfx x21, x21, #30, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror rax, 1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xd1 /1",
|
|
"ExpectedArm64ASM": [
|
|
"ror x4, x4, #1",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"lsr x21, x4, #63",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"eor x21, x4, x4, lsr #1",
|
|
"ubfx x21, x21, #62, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl ax, 1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": "GROUP2 0xd1 /2",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"cset w21, hs",
|
|
"orr w21, w21, w20, lsl #1",
|
|
"bfxil x4, x21, #0, #16",
|
|
"ubfx x22, x20, #15, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w22, #29, #1",
|
|
"mov w22, w0",
|
|
"eor w20, w21, w20",
|
|
"ubfx x20, x20, #15, #1",
|
|
"mov w0, w22",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl eax, 1": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xd1 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"cset w21, hs",
|
|
"orr w4, w21, w20, lsl #1",
|
|
"ubfx x21, x20, #31, #1",
|
|
"mrs x22, nzcv",
|
|
"mov w0, w22",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"eor w20, w4, w20",
|
|
"ubfx x20, x20, #31, #1",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl rax, 1": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xd1 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"cset w21, hs",
|
|
"orr x4, x21, x20, lsl #1",
|
|
"lsr x21, x20, #63",
|
|
"mrs x22, nzcv",
|
|
"mov w0, w22",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"eor x20, x4, x20",
|
|
"lsr x20, x20, #63",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr ax, 1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": "GROUP2 0xd1 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"ubfx x21, x4, #0, #1",
|
|
"mrs x22, nzcv",
|
|
"mov w0, w22",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"ubfx w22, w4, #1, #15",
|
|
"orr w20, w22, w20, lsl #15",
|
|
"bfxil x4, x20, #0, #16",
|
|
"eor x20, x20, x20, lsr #1",
|
|
"ubfx x20, x20, #14, #1",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr eax, 1": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xd1 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"ubfx x21, x4, #0, #1",
|
|
"mrs x22, nzcv",
|
|
"mov w0, w22",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"extr w4, w20, w4, #1",
|
|
"eor x20, x4, x4, lsr #1",
|
|
"ubfx x20, x20, #30, #1",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr rax, 1": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xd1 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"ubfx x21, x4, #0, #1",
|
|
"mrs x22, nzcv",
|
|
"mov w0, w22",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"extr x4, x20, x4, #1",
|
|
"eor x20, x4, x4, lsr #1",
|
|
"ubfx x20, x20, #62, #1",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl ax, 1": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xd1 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"lsl w21, w20, #1",
|
|
"bfxil x4, x21, #0, #16",
|
|
"uxth w26, w21",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #15, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w26, w20",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl eax, 1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": "GROUP2 0xd1 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"lsl w4, w20, #1",
|
|
"tst w4, w4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #31, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"mov x26, x4",
|
|
"eor w20, w4, w20",
|
|
"ubfx x20, x20, #31, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl rax, 1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": "GROUP2 0xd1 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsl x4, x20, #1",
|
|
"tst x4, x4",
|
|
"mrs x21, nzcv",
|
|
"lsr x22, x20, #63",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"mov x26, x4",
|
|
"eor x20, x4, x20",
|
|
"lsr x20, x20, #63",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr ax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xd1 /5",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"lsr w26, w20, #1",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr eax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xd1 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"lsr w4, w20, #1",
|
|
"tst w4, w4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"mov x26, x4",
|
|
"ubfx x20, x20, #31, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr rax, 1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xd1 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsr x4, x20, #1",
|
|
"tst x4, x4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"mov x26, x4",
|
|
"lsr x20, x20, #63",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar ax, 1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xd1 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"sxth x20, w20",
|
|
"asr w26, w20, #1",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cmn wzr, w26, lsl #16",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar eax, 1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xd1 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"asr w4, w20, #1",
|
|
"tst w4, w4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar rax, 1": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xd1 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"asr x4, x20, #1",
|
|
"tst x4, x4",
|
|
"mrs x21, nzcv",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #29",
|
|
"mov x26, x4",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol al, cl": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "GROUP2 0xd2 /0",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxtb w21, w5",
|
|
"and w21, w21, #0x1f",
|
|
"bfi w20, w20, #8, #8",
|
|
"bfi w20, w20, #16, #16",
|
|
"mov w22, #0x20",
|
|
"sub w22, w22, w21",
|
|
"ror w20, w20, w22",
|
|
"bfxil x4, x20, #0, #8",
|
|
"cbz x21, #+0x24",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #7",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror al, cl": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd2 /1",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxtb w21, w5",
|
|
"and w21, w21, #0x1f",
|
|
"bfi w20, w20, #8, #8",
|
|
"bfi w20, w20, #16, #16",
|
|
"ror w20, w20, w21",
|
|
"bfxil x4, x20, #0, #8",
|
|
"cbz x21, #+0x24",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #7, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #1",
|
|
"ubfx x20, x20, #6, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl al, cl": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Comment": "GROUP2 0xd2 /2",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"and w21, w5, #0x1f",
|
|
"cbz x21, #+0x88",
|
|
"uxtb w22, w4",
|
|
"mov w23, #0x0",
|
|
"bfi x23, x22, #55, #8",
|
|
"bfi x23, x20, #63, #1",
|
|
"bfi x23, x22, #46, #8",
|
|
"bfi x23, x20, #54, #1",
|
|
"bfi x23, x22, #37, #8",
|
|
"bfi x23, x20, #45, #1",
|
|
"bfi x23, x22, #28, #8",
|
|
"bfi x23, x20, #36, #1",
|
|
"bfi x23, x22, #19, #8",
|
|
"mov x0, x23",
|
|
"bfi x0, x20, #27, #1",
|
|
"mov x20, x0",
|
|
"bfxil x20, x22, #0, #8",
|
|
"mov w22, #0x40",
|
|
"sub w22, w22, w21",
|
|
"ror x22, x20, x22",
|
|
"bfxil x4, x22, #0, #8",
|
|
"mov w23, #0x3f",
|
|
"sub x21, x23, x21",
|
|
"ror x20, x20, x21",
|
|
"ubfx x21, x20, #0, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"eor x20, x20, x22, lsr #7",
|
|
"ubfx x20, x20, #0, #1",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr al, cl": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Comment": "GROUP2 0xd2 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"and w21, w5, #0x1f",
|
|
"cbz x21, #+0x54",
|
|
"uxtb w22, w4",
|
|
"mov x0, x22",
|
|
"bfi x0, x20, #8, #1",
|
|
"mov x20, x0",
|
|
"bfi x20, x20, #9, #9",
|
|
"bfi x20, x20, #18, #18",
|
|
"bfi x20, x20, #36, #9",
|
|
"lsr x22, x20, x21",
|
|
"bfxil x4, x22, #0, #8",
|
|
"sub w21, w21, #0x1 (1)",
|
|
"lsr x20, x20, x21",
|
|
"ubfx x20, x20, #0, #1",
|
|
"mrs x21, nzcv",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"eor x21, x22, x22, lsr #1",
|
|
"ubfx x21, x21, #6, #1",
|
|
"bfi w20, w21, #28, #1",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl al, cl": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "GROUP2 0xd2 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxtb w21, w5",
|
|
"lsl w22, w20, w21",
|
|
"bfxil x4, x22, #0, #8",
|
|
"uxtb w22, w22",
|
|
"cbz x21, #+0x34",
|
|
"cmn wzr, w22, lsl #24",
|
|
"mrs x23, nzcv",
|
|
"mov w24, #0x8",
|
|
"sub w21, w24, w21",
|
|
"lsr w21, w20, w21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor w20, w20, w22",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr al, cl": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd2 /5",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxtb w21, w5",
|
|
"lsr w22, w20, w21",
|
|
"bfxil x4, x22, #0, #8",
|
|
"cbz x21, #+0x30",
|
|
"cmn wzr, w22, lsl #24",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr w21, w20, w21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor w20, w20, w22",
|
|
"ubfx x20, x20, #7, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar al, cl": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xd2 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxtb w21, w5",
|
|
"sxtb x20, w20",
|
|
"asr w22, w20, w21",
|
|
"bfxil x4, x22, #0, #8",
|
|
"cbz x21, #+0x24",
|
|
"cmn wzr, w22, lsl #24",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr x20, x20, x21",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w23, w20, lsl #29",
|
|
"mov x26, x22",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol ax, cl": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "GROUP2 0xd3 /0",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"uxth w21, w5",
|
|
"and w21, w21, #0x1f",
|
|
"bfi w20, w20, #16, #16",
|
|
"mov w22, #0x20",
|
|
"sub w22, w22, w21",
|
|
"ror w20, w20, w22",
|
|
"bfxil x4, x20, #0, #16",
|
|
"cbz x21, #+0x24",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #15",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol eax, cl": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd3 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, w5",
|
|
"and w21, w21, #0x1f",
|
|
"mov w22, #0x20",
|
|
"sub w22, w22, w21",
|
|
"ror w20, w20, w22",
|
|
"mov x4, x20",
|
|
"cbz x21, #+0x24",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #0, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #31",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rol rax, cl": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xd3 /0",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x5, #0x3f",
|
|
"mov w21, #0x40",
|
|
"sub x21, x21, x20",
|
|
"ror x21, x4, x21",
|
|
"mov x4, x21",
|
|
"cbz x20, #+0x24",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"ubfx x22, x21, #0, #1",
|
|
"orr w20, w20, w22, lsl #29",
|
|
"eor x21, x21, x21, lsr #63",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror ax, cl": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": "GROUP2 0xd3 /1",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"uxth w21, w5",
|
|
"and w21, w21, #0x1f",
|
|
"bfi w20, w20, #16, #16",
|
|
"ror w20, w20, w21",
|
|
"bfxil x4, x20, #0, #16",
|
|
"cbz x21, #+0x24",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #15, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #1",
|
|
"ubfx x20, x20, #14, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror eax, cl": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xd3 /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, w5",
|
|
"and w21, w21, #0x1f",
|
|
"ror w20, w20, w21",
|
|
"mov x4, x20",
|
|
"cbz x21, #+0x24",
|
|
"mrs x21, nzcv",
|
|
"and w21, w21, #0xc0000000",
|
|
"ubfx x22, x20, #31, #1",
|
|
"orr w21, w21, w22, lsl #29",
|
|
"eor w20, w20, w20, lsr #1",
|
|
"ubfx x20, x20, #30, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"ror rax, cl": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xd3 /1",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x5, #0x3f",
|
|
"ror x21, x4, x20",
|
|
"mov x4, x21",
|
|
"cbz x20, #+0x24",
|
|
"mrs x20, nzcv",
|
|
"and w20, w20, #0xc0000000",
|
|
"lsr x22, x21, #63",
|
|
"orr w20, w20, w22, lsl #29",
|
|
"eor x21, x21, x21, lsr #1",
|
|
"ubfx x21, x21, #62, #1",
|
|
"orr w20, w20, w21, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl ax, cl": {
|
|
"ExpectedInstructionCount": 32,
|
|
"Comment": "GROUP2 0xd3 /2",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"and w21, w5, #0x1f",
|
|
"cbz x21, #+0x78",
|
|
"uxth w22, w4",
|
|
"mov w23, #0x0",
|
|
"bfi x23, x22, #47, #16",
|
|
"bfi x23, x20, #63, #1",
|
|
"bfi x23, x22, #30, #16",
|
|
"bfi x23, x20, #46, #1",
|
|
"bfi x23, x22, #13, #16",
|
|
"mov x0, x23",
|
|
"bfi x0, x20, #29, #1",
|
|
"mov x20, x0",
|
|
"bfxil x20, x22, #0, #16",
|
|
"mov w22, #0x40",
|
|
"sub w22, w22, w21",
|
|
"ror x22, x20, x22",
|
|
"bfxil x4, x22, #0, #16",
|
|
"mov w23, #0x3f",
|
|
"sub x21, x23, x21",
|
|
"ror x20, x20, x21",
|
|
"ubfx x21, x20, #0, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w21, #29, #1",
|
|
"mov w21, w0",
|
|
"eor x20, x20, x22, lsr #15",
|
|
"ubfx x20, x20, #0, #1",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl eax, cl": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Comment": "GROUP2 0xd3 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsl w21, w20, w5",
|
|
"cset w22, hs",
|
|
"and w23, w5, #0x1f",
|
|
"cbz x23, #+0x4c",
|
|
"neg w24, w23",
|
|
"lsr w25, w20, w24",
|
|
"orr w21, w21, w25, lsr #1",
|
|
"lsr w20, w20, w24",
|
|
"ubfx x24, x20, #0, #1",
|
|
"mrs x25, nzcv",
|
|
"mov w0, w25",
|
|
"bfi w0, w24, #29, #1",
|
|
"mov w24, w0",
|
|
"sub w23, w23, #0x1 (1)",
|
|
"lsl x22, x22, x23",
|
|
"orr w4, w21, w22",
|
|
"eor w20, w4, w20, lsl #31",
|
|
"ubfx x20, x20, #31, #1",
|
|
"mov w0, w24",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcl rax, cl": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Comment": "GROUP2 0xd3 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsl x21, x20, x5",
|
|
"cset w22, hs",
|
|
"and x23, x5, #0x3f",
|
|
"cbz x23, #+0x4c",
|
|
"neg x24, x23",
|
|
"lsr x25, x20, x24",
|
|
"orr x21, x21, x25, lsr #1",
|
|
"lsr x20, x20, x24",
|
|
"ubfx x24, x20, #0, #1",
|
|
"mrs x25, nzcv",
|
|
"mov w0, w25",
|
|
"bfi w0, w24, #29, #1",
|
|
"mov w24, w0",
|
|
"sub x23, x23, #0x1 (1)",
|
|
"lsl x22, x22, x23",
|
|
"orr x4, x21, x22",
|
|
"eor x20, x4, x20, lsl #63",
|
|
"lsr x20, x20, #63",
|
|
"mov w0, w24",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr ax, cl": {
|
|
"ExpectedInstructionCount": 22,
|
|
"Comment": "GROUP2 0xd3 /3",
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"and w21, w5, #0x1f",
|
|
"cbz x21, #+0x50",
|
|
"uxth w22, w4",
|
|
"mov x0, x22",
|
|
"bfi x0, x20, #16, #1",
|
|
"mov x20, x0",
|
|
"bfi x20, x20, #17, #17",
|
|
"bfi x20, x20, #34, #17",
|
|
"lsr x22, x20, x21",
|
|
"bfxil x4, x22, #0, #16",
|
|
"sub w21, w21, #0x1 (1)",
|
|
"lsr x20, x20, x21",
|
|
"ubfx x20, x20, #0, #1",
|
|
"mrs x21, nzcv",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"eor x21, x22, x22, lsr #1",
|
|
"ubfx x21, x21, #14, #1",
|
|
"bfi w20, w21, #28, #1",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr eax, cl": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Comment": "GROUP2 0xd3 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsr w21, w20, w5",
|
|
"cset w22, hs",
|
|
"and w23, w5, #0x1f",
|
|
"cbz x23, #+0x44",
|
|
"neg w24, w23",
|
|
"lsl w25, w20, w24",
|
|
"orr w21, w21, w25, lsl #1",
|
|
"sub w23, w23, #0x1 (1)",
|
|
"lsr w20, w20, w23",
|
|
"ubfx x20, x20, #0, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"lsl w22, w22, w24",
|
|
"orr w4, w21, w22",
|
|
"eor w21, w4, w4, lsr #1",
|
|
"ubfx x21, x21, #30, #1",
|
|
"bfi w20, w21, #28, #1",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"rcr rax, cl": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Comment": "GROUP2 0xd3 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"lsr x21, x20, x5",
|
|
"cset w22, hs",
|
|
"and x23, x5, #0x3f",
|
|
"cbz x23, #+0x44",
|
|
"neg x24, x23",
|
|
"lsl x25, x20, x24",
|
|
"orr x21, x21, x25, lsl #1",
|
|
"sub x23, x23, #0x1 (1)",
|
|
"lsr x20, x20, x23",
|
|
"ubfx x20, x20, #0, #1",
|
|
"mrs x23, nzcv",
|
|
"mov w0, w23",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"lsl x22, x22, x24",
|
|
"orr x4, x21, x22",
|
|
"eor x21, x4, x4, lsr #1",
|
|
"ubfx x21, x21, #62, #1",
|
|
"bfi w20, w21, #28, #1",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl ax, cl": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Comment": "GROUP2 0xd3 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"uxth w21, w5",
|
|
"lsl w22, w20, w21",
|
|
"bfxil x4, x22, #0, #16",
|
|
"uxth w22, w22",
|
|
"cbz x21, #+0x34",
|
|
"cmn wzr, w22, lsl #16",
|
|
"mrs x23, nzcv",
|
|
"mov w24, #0x10",
|
|
"sub w21, w24, w21",
|
|
"lsr w21, w20, w21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor w20, w20, w22",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl eax, cl": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "GROUP2 0xd3 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, w5",
|
|
"lsl w22, w20, w21",
|
|
"mov x4, x22",
|
|
"cbz x21, #+0x34",
|
|
"tst w22, w22",
|
|
"mrs x23, nzcv",
|
|
"mov w24, #0x20",
|
|
"sub w21, w24, w21",
|
|
"lsr w21, w20, w21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor w20, w20, w22",
|
|
"ubfx x20, x20, #31, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shl rax, cl": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Comment": "GROUP2 0xd3 /4",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"mov x21, x5",
|
|
"lsl x22, x20, x21",
|
|
"mov x4, x22",
|
|
"cbz x21, #+0x34",
|
|
"tst x22, x22",
|
|
"mrs x23, nzcv",
|
|
"mov w24, #0x40",
|
|
"sub x21, x24, x21",
|
|
"lsr x21, x20, x21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor x20, x20, x22",
|
|
"lsr x20, x20, #63",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr ax, cl": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd3 /5",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"uxth w21, w5",
|
|
"lsr w22, w20, w21",
|
|
"bfxil x4, x22, #0, #16",
|
|
"cbz x21, #+0x30",
|
|
"cmn wzr, w22, lsl #16",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr w21, w20, w21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor w20, w20, w22",
|
|
"ubfx x20, x20, #15, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr eax, cl": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd3 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, w5",
|
|
"lsr w22, w20, w21",
|
|
"mov x4, x22",
|
|
"cbz x21, #+0x30",
|
|
"tst w22, w22",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr w21, w20, w21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor w20, w20, w22",
|
|
"ubfx x20, x20, #31, #1",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"shr rax, cl": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": "GROUP2 0xd3 /5",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"mov x21, x5",
|
|
"lsr x22, x20, x21",
|
|
"mov x4, x22",
|
|
"cbz x21, #+0x30",
|
|
"tst x22, x22",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr x21, x20, x21",
|
|
"ubfx x21, x21, #0, #1",
|
|
"orr w21, w23, w21, lsl #29",
|
|
"mov x26, x22",
|
|
"eor x20, x20, x22",
|
|
"lsr x20, x20, #63",
|
|
"orr w20, w21, w20, lsl #28",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar ax, cl": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xd3 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"uxth w21, w5",
|
|
"sxth x20, w20",
|
|
"asr w22, w20, w21",
|
|
"bfxil x4, x22, #0, #16",
|
|
"cbz x21, #+0x24",
|
|
"cmn wzr, w22, lsl #16",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr x20, x20, x21",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w23, w20, lsl #29",
|
|
"mov x26, x22",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar eax, cl": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xd3 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, w5",
|
|
"asr w22, w20, w21",
|
|
"mov x4, x22",
|
|
"cbz x21, #+0x24",
|
|
"tst w22, w22",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr w20, w20, w21",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w23, w20, lsl #29",
|
|
"mov x26, x22",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"sar rax, cl": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xd3 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"mov x21, x5",
|
|
"asr x22, x20, x21",
|
|
"mov x4, x22",
|
|
"cbz x21, #+0x24",
|
|
"tst x22, x22",
|
|
"mrs x23, nzcv",
|
|
"sub x21, x21, #0x1 (1)",
|
|
"lsr x20, x20, x21",
|
|
"ubfx x20, x20, #0, #1",
|
|
"orr w20, w23, w20, lsl #29",
|
|
"mov x26, x22",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"test bl, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP2 0xf6 /0",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w7, #0x1",
|
|
"cmn wzr, w26, lsl #24"
|
|
]
|
|
},
|
|
"not bl": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf6 /2",
|
|
"ExpectedArm64ASM": [
|
|
"eor x7, x7, #0xff"
|
|
]
|
|
},
|
|
"not bh": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf6 /2",
|
|
"ExpectedArm64ASM": [
|
|
"eor x7, x7, #0xff00"
|
|
]
|
|
},
|
|
"neg bl": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xf6 /3",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w27, w7",
|
|
"cmp wzr, w27, lsl #24",
|
|
"neg w26, w27",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x7, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"mul bl": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xf6 /4",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb x20, w7",
|
|
"uxtb x21, w4",
|
|
"mul x20, x20, x21",
|
|
"bfxil x4, x20, #0, #16",
|
|
"ubfx x20, x20, #8, #8",
|
|
"cmp x20, #0x0 (0)",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul bl": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xf6 /5",
|
|
"ExpectedArm64ASM": [
|
|
"sxtb x20, w7",
|
|
"sxtb x21, w4",
|
|
"mul x20, x20, x21",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sbfx x21, x20, #8, #8",
|
|
"sbfx x20, x20, #7, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"div bl": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Comment": "GROUP2 0xf6 /6",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w7",
|
|
"uxth w21, w4",
|
|
"uxth w0, w21",
|
|
"uxth w1, w20",
|
|
"udiv w22, w0, w1",
|
|
"uxth w0, w21",
|
|
"uxth w1, w20",
|
|
"udiv w2, w0, w1",
|
|
"msub w20, w2, w1, w0",
|
|
"mov x0, x22",
|
|
"bfi x0, x20, #8, #8",
|
|
"mov x20, x0",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"idiv bl": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": "GROUP2 0xf6 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w7",
|
|
"uxth w21, w4",
|
|
"sxth x21, w21",
|
|
"sxtb x20, w20",
|
|
"sdiv x22, x21, x20",
|
|
"sdiv x0, x21, x20",
|
|
"msub x20, x0, x20, x21",
|
|
"mov x0, x22",
|
|
"bfi x0, x20, #8, #8",
|
|
"mov x20, x0",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"test bx, 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP2 0xf7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"and w26, w7, #0x1",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"test ebx, 1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w7, #0x1"
|
|
]
|
|
},
|
|
"test rbx, 1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x7, #0x1"
|
|
]
|
|
},
|
|
"test bx, -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP2 0xf7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x26, x7",
|
|
"cmn wzr, w26, lsl #16"
|
|
]
|
|
},
|
|
"test ebx, -1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ands w26, w7, w7"
|
|
]
|
|
},
|
|
"test rbx, -1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"ands x26, x7, x7"
|
|
]
|
|
},
|
|
"not bx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /1",
|
|
"ExpectedArm64ASM": [
|
|
"eor x7, x7, #0xffff"
|
|
]
|
|
},
|
|
"not ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /1",
|
|
"ExpectedArm64ASM": [
|
|
"mvn w7, w7"
|
|
]
|
|
},
|
|
"not rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP2 0xf7 /1",
|
|
"ExpectedArm64ASM": [
|
|
"mvn x7, x7"
|
|
]
|
|
},
|
|
"neg bx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xf7 /2",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w27, w7",
|
|
"cmp wzr, w27, lsl #16",
|
|
"neg w26, w27",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"bfxil x7, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"neg ebx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP2 0xf7 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov w27, w7",
|
|
"negs w26, w27",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x7, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"neg rbx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "GROUP2 0xf7 /2",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x7",
|
|
"negs x26, x27",
|
|
"mrs x20, nzcv",
|
|
"eor w20, w20, #0x20000000",
|
|
"mov x7, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"mul bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "GROUP2 0xf7 /3",
|
|
"ExpectedArm64ASM": [
|
|
"uxth x20, w7",
|
|
"uxth x21, w4",
|
|
"mul x20, x20, x21",
|
|
"bfxil x4, x20, #0, #16",
|
|
"ubfx x20, x20, #16, #16",
|
|
"bfxil x6, x20, #0, #16",
|
|
"cmp x20, #0x0 (0)",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"mul ebx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "GROUP2 0xf7 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w7",
|
|
"mov w21, w4",
|
|
"mul x20, x20, x21",
|
|
"mov w4, w20",
|
|
"lsr x6, x20, #32",
|
|
"cmp x6, #0x0 (0)",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"mul rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "GROUP2 0xf7 /3",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"mul x4, x7, x20",
|
|
"umulh x6, x7, x20",
|
|
"cmp x6, #0x0 (0)",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul bx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP2 0xf7 /5",
|
|
"ExpectedArm64ASM": [
|
|
"sxth x20, w7",
|
|
"sxth x21, w4",
|
|
"mul x20, x20, x21",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sbfx x21, x20, #16, #16",
|
|
"bfxil x6, x21, #0, #16",
|
|
"sbfx x20, x20, #15, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul ebx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP2 0xf7 /5",
|
|
"ExpectedArm64ASM": [
|
|
"sxtw x20, w7",
|
|
"sxtw x21, w4",
|
|
"mul x20, x20, x21",
|
|
"mov w4, w20",
|
|
"lsr x6, x20, #32",
|
|
"asr x21, x20, #32",
|
|
"sxtw x20, w20",
|
|
"sbfx x20, x20, #31, #1",
|
|
"cmp x21, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"imul rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "GROUP2 0xf7 /5",
|
|
"ExpectedArm64ASM": [
|
|
"smulh x6, x7, x4",
|
|
"mul x4, x7, x4",
|
|
"asr x20, x4, #63",
|
|
"cmp x6, x20",
|
|
"ccmn xzr, #0, #nzCV, eq"
|
|
]
|
|
},
|
|
"div bx": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xf7 /6",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w7",
|
|
"uxth w21, w4",
|
|
"uxth w22, w6",
|
|
"uxth w0, w21",
|
|
"bfi w0, w22, #16, #16",
|
|
"udiv w23, w0, w20",
|
|
"uxth w0, w21",
|
|
"bfi w0, w22, #16, #16",
|
|
"udiv w1, w0, w20",
|
|
"msub w20, w1, w20, w0",
|
|
"bfxil x4, x23, #0, #16",
|
|
"bfxil x6, x20, #0, #16"
|
|
]
|
|
},
|
|
"div ebx": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Comment": "GROUP2 0xf7 /6",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w7",
|
|
"mov w21, w4",
|
|
"mov w22, w6",
|
|
"mov x0, x21",
|
|
"bfi x0, x22, #32, #32",
|
|
"udiv x23, x0, x20",
|
|
"mov w4, w23",
|
|
"mov x0, x21",
|
|
"bfi x0, x22, #32, #32",
|
|
"udiv x1, x0, x20",
|
|
"msub x20, x1, x20, x0",
|
|
"mov w6, w20"
|
|
]
|
|
},
|
|
"div rbx": {
|
|
"ExpectedInstructionCount": 24,
|
|
"Comment": "GROUP2 0xf7 /6",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"cbz x6, #+0x28",
|
|
"mov x0, x6",
|
|
"mov x1, x20",
|
|
"mov x2, x7",
|
|
"ldr x3, [x28, #2224]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x3",
|
|
"ldr x30, [sp], #16",
|
|
"mov x4, x0",
|
|
"b #+0x8",
|
|
"udiv x4, x20, x7",
|
|
"cbz x6, #+0x28",
|
|
"mov x0, x6",
|
|
"mov x1, x20",
|
|
"mov x2, x7",
|
|
"ldr x3, [x28, #2240]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x3",
|
|
"ldr x30, [sp], #16",
|
|
"mov x6, x0",
|
|
"b #+0xc",
|
|
"udiv x0, x20, x7",
|
|
"msub x6, x0, x7, x20"
|
|
]
|
|
},
|
|
"idiv bx": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xf7 /7",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w7",
|
|
"uxth w21, w4",
|
|
"uxth w22, w6",
|
|
"uxth w0, w21",
|
|
"bfi w0, w22, #16, #16",
|
|
"sxth w1, w20",
|
|
"sdiv w23, w0, w1",
|
|
"uxth w0, w21",
|
|
"bfi w0, w22, #16, #16",
|
|
"sxth w1, w20",
|
|
"sdiv w2, w0, w1",
|
|
"msub w20, w2, w1, w0",
|
|
"bfxil x4, x23, #0, #16",
|
|
"bfxil x6, x20, #0, #16"
|
|
]
|
|
},
|
|
"idiv ebx": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": "GROUP2 0xf7 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w7",
|
|
"mov w21, w4",
|
|
"mov w22, w6",
|
|
"mov x0, x21",
|
|
"bfi x0, x22, #32, #32",
|
|
"sxtw x1, w20",
|
|
"sdiv x23, x0, x1",
|
|
"mov w4, w23",
|
|
"mov x0, x21",
|
|
"bfi x0, x22, #32, #32",
|
|
"sxtw x2, w20",
|
|
"sdiv x1, x0, x2",
|
|
"msub x20, x1, x2, x0",
|
|
"mov w6, w20"
|
|
]
|
|
},
|
|
"idiv rbx": {
|
|
"ExpectedInstructionCount": 28,
|
|
"Comment": "GROUP2 0xf7 /7",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"asr x0, x20, #63",
|
|
"eor x0, x0, x6",
|
|
"cbz x0, #+0x28",
|
|
"mov x0, x6",
|
|
"mov x1, x20",
|
|
"mov x2, x7",
|
|
"ldr x3, [x28, #2232]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x3",
|
|
"ldr x30, [sp], #16",
|
|
"mov x4, x0",
|
|
"b #+0x8",
|
|
"sdiv x4, x20, x7",
|
|
"asr x0, x20, #63",
|
|
"eor x0, x0, x6",
|
|
"cbz x0, #+0x28",
|
|
"mov x0, x6",
|
|
"mov x1, x20",
|
|
"mov x2, x7",
|
|
"ldr x3, [x28, #2248]",
|
|
"str x30, [sp, #-16]!",
|
|
"blr x3",
|
|
"ldr x30, [sp], #16",
|
|
"mov x6, x0",
|
|
"b #+0xc",
|
|
"sdiv x0, x20, x7",
|
|
"msub x6, x0, x7, x20"
|
|
]
|
|
},
|
|
"inc al": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP3 0xfe /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"uxtb w27, w4",
|
|
"cset w21, hs",
|
|
"lsl w0, w27, #24",
|
|
"cmn w0, w20, lsl #24",
|
|
"add w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"bfi w20, w21, #29, #1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"dec al": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP3 0xfe /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"uxtb w27, w4",
|
|
"cset w21, hs",
|
|
"lsl w0, w27, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"bfi w20, w21, #29, #1",
|
|
"bfxil x4, x26, #0, #8",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"inc ax": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP4 0xfe /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"uxth w27, w4",
|
|
"cset w21, hs",
|
|
"lsl w0, w27, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"bfi w20, w21, #29, #1",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"inc eax": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP4 0xfe /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"cset w20, hs",
|
|
"adds w26, w27, #0x1 (1)",
|
|
"mrs x21, nzcv",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"inc rax": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP4 0xfe /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"cset w20, hs",
|
|
"adds x26, x27, #0x1 (1)",
|
|
"mrs x21, nzcv",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"dec ax": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "GROUP4 0xfe /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"uxth w27, w4",
|
|
"cset w21, hs",
|
|
"lsl w0, w27, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w27, #0x1 (1)",
|
|
"mrs x20, nzcv",
|
|
"bfi w20, w21, #29, #1",
|
|
"bfxil x4, x26, #0, #16",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"dec eax": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP4 0xfe /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"cset w20, hs",
|
|
"subs w26, w27, #0x1 (1)",
|
|
"mrs x21, nzcv",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"dec rax": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "GROUP4 0xfe /1",
|
|
"ExpectedArm64ASM": [
|
|
"mov x27, x4",
|
|
"cset w20, hs",
|
|
"subs x26, x27, #0x1 (1)",
|
|
"mrs x21, nzcv",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"mov x4, x26",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"push ax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP4 0xff /6",
|
|
"ExpectedArm64ASM": [
|
|
"strh w4, [x8, #-2]!"
|
|
]
|
|
},
|
|
"push rax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "GROUP4 0xff /6",
|
|
"ExpectedArm64ASM": [
|
|
"str x4, [x8, #-8]!"
|
|
]
|
|
},
|
|
"mov byte [rax], 0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc6 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"strb w20, [x4]"
|
|
]
|
|
},
|
|
"mov word [rax], 0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"mov dword [rax], 0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"str w20, [x4]"
|
|
]
|
|
},
|
|
"mov qword [rax], 0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x0",
|
|
"str x20, [x4]"
|
|
]
|
|
},
|
|
"mov byte [rax], 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc6 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"strb w20, [x4]"
|
|
]
|
|
},
|
|
"mov word [rax], 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"mov dword [rax], 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"str w20, [x4]"
|
|
]
|
|
},
|
|
"mov qword [rax], 1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"str x20, [x4]"
|
|
]
|
|
},
|
|
"mov byte [rax], -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc6 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xff",
|
|
"strb w20, [x4]"
|
|
]
|
|
},
|
|
"mov word [rax], -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffff",
|
|
"strh w20, [x4]"
|
|
]
|
|
},
|
|
"mov dword [rax], -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0xffffffff",
|
|
"str w20, [x4]"
|
|
]
|
|
},
|
|
"mov qword [rax], -1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "GROUP11 0xc7 /0",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffffff",
|
|
"str x20, [x4]"
|
|
]
|
|
}
|
|
}
|
|
}
|