Files
FEX-Emu--FEX/External/FEXCore/Source/Interface/Core
Scott Mansell 5119a0bdb3 Elimiante ALU IR nodes that don't zero extend
Add and substract were the main culprits here.

We are trying to more towards a state where:
  * Every IR op can expect it isn't given extra bits
     on it's input
  * Every IR op never sets more bits than it's size
  * All unnessicary BFEs are never emitted
  * ARM doesn't have to implement special 8 and 16bit versions of IR ops
      All masking required to implement 8/16bit math on
      arm should be explictly generated from Opcode decoder
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