Ryan Houdek 74e2f189f1 Implements MASKMOVQ and MASKMOVDQU ...

Without supporting phis this entire loop needs to be unrolled.

I just found out while reading the x86 documentation that this
instruction is explicitly a weakly ordered memory operation.
So this operation can be changed over to a couple vector conditional
loadstores soon after merging

2020-09-22 23:23:51 -07:00

..

Config

SMC: Add --smc-full-checks, implement frontend, irint, irjit, unit test

2020-09-16 01:15:21 +03:00

Context

Adds ability for the frontend to register a signal handler

2020-09-22 13:19:41 -07:00

Core

Implements MASKMOVQ and MASKMOVDQU

2020-09-22 23:23:51 -07:00

HLE

Merge pull request #396 from FEX-Emu/skmp/execve-only-existing-files

2020-09-22 15:25:08 -07:00

IR

Fixes crash when SSA value has size of zero

2020-09-22 18:20:32 -07:00

Memory

[WIP] Fork syscall support

2020-06-30 16:22:47 +03:00