Alyssa Rosenzweig 99446da7c1 JIT: add Reg helpers taking OrderedNodeWrappers ...

more ergonomic and will give us freedom to migrate things easier soon.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2025-05-14 15:43:20 -04:00

..

ALUOps.cpp

OpcodeDispatcher: Implement support for self-synchronizing cycle counter

2025-04-15 15:42:43 -07:00

Arm64Relocations.cpp

Drop use of assume-asserting logging macros

2025-01-21 12:01:33 +01:00

AtomicOps.cpp

Various: More static analysis warnings cleanup

2025-03-12 17:27:41 -07:00

BranchOps.cpp

JIT: Make code patching during (un-/)linking thread-safe

2025-04-25 09:21:09 +02:00

ConversionOps.cpp

JIT: Fix warning about unused variable

2025-04-18 11:16:46 +02:00

EncryptionOps.cpp

IR: Implement support for sha256h{2,}

2025-04-01 17:53:48 -07:00

JIT.cpp

Merge pull request #4542 from Sonicadvance1/fexcore_reconstructions_getting_saved_today

2025-05-01 13:28:16 -04:00

JITClass.h

JIT: add Reg helpers taking OrderedNodeWrappers

2025-05-14 15:43:20 -04:00

MemoryOps.cpp

Merge pull request #4438 from Sonicadvance1/static_analysis_wars

2025-03-27 20:30:37 -07:00

MiscOps.cpp

OpcodeDispatcher: Fix CPUID being a instruction fence

2025-04-15 15:42:43 -07:00

MoveOps.cpp

JIT: Moves Arm64 JIT up one folder

2024-10-25 18:44:20 -07:00

VectorOps.cpp

IR: allow VUShrNI with bitshift=0

2025-03-31 16:03:18 -04:00