Alyssa Rosenzweig 99854ff310 JIT: add GetZeroableReg helper ...

for inlining constant zeroes in applicable sources

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-02-24 15:54:49 -04:00

..

Common

FEXCore: Moves BitUtils to FHU

2023-12-25 06:38:51 -08:00

Interface

JIT: add GetZeroableReg helper

2024-02-24 15:54:49 -04:00

Utils

SpinWaitLock: Removes unused variable in spin-loop fallback

2024-02-05 07:22:52 -08:00

CMakeLists.txt

FEXCore/Utils: Rename FutexSpinWait to SpinWaitLock

2024-01-17 10:19:38 -08:00