FEX-Emu--FEX/unittests/InstructionCountCI/FlagM/Primary.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "FLAGM",
      "FLAGM2"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP"
    ]
  },
  "Instructions": {
    "add bl, cl": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x00",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "lsl w0, w7, #24",
        "cmn w0, w5, lsl #24",
        "add w26, w7, w5",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "add bx, cx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x01",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "lsl w0, w7, #16",
        "cmn w0, w5, lsl #16",
        "add w26, w7, w5",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "add ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x01",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "adds w26, w7, w5",
        "mov x7, x26"
      ]
    },
    "add rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x01",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "adds x26, x7, x5",
        "mov x7, x26"
      ]
    },
    "db 0x02, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x02",
        "add bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "lsl w0, w5, #24",
        "cmn w0, w7, lsl #24",
        "add w26, w5, w7",
        "bfxil x5, x26, #0, #8"
      ]
    },
    "db 0x66, 0x03, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x03",
        "add bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "lsl w0, w5, #16",
        "cmn w0, w7, lsl #16",
        "add w26, w5, w7",
        "bfxil x5, x26, #0, #16"
      ]
    },
    "db 0x03, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x03",
        "add ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "adds w26, w5, w7",
        "mov x5, x26"
      ]
    },
    "db 0x48, 0x03, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x03",
        "add rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "adds x26, x5, x7",
        "mov x5, x26"
      ]
    },
    "add al, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x04",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "lsl w0, w4, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w4, #0x1 (1)",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "add ax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, #0x1 (1)",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "add eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "adds w26, w4, #0x1 (1)",
        "mov x4, x26"
      ]
    },
    "add rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "adds x26, x4, #0x1 (1)",
        "mov x4, x26"
      ]
    },
    "add al, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x04",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w4, #0xff (255)",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "add ax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, w20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "add eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "adds w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "add rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "subs x26, x4, #0x1 (1)",
        "mov x4, x26"
      ]
    },
    "or bl, bh": {
      "ExpectedInstructionCount": 4,
      "Comment": "",
      "ExpectedArm64ASM": [
        "lsr w20, w7, #8",
        "orr w26, w7, w20",
        "bfxil x7, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "or bl, cl": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x08",
      "ExpectedArm64ASM": [
        "orr w26, w7, w5",
        "bfxil x7, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "or bx, cx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x09",
      "ExpectedArm64ASM": [
        "orr w26, w7, w5",
        "bfxil x7, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "or ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x09",
      "ExpectedArm64ASM": [
        "orr w7, w7, w5",
        "mov x26, x7",
        "tst w7, w7"
      ]
    },
    "or rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x09",
      "ExpectedArm64ASM": [
        "orr x7, x7, x5",
        "mov x26, x7",
        "tst x7, x7"
      ]
    },
    "db 0x0A, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x0A",
        "or bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr w26, w5, w7",
        "bfxil x5, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "db 0x66, 0x0B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x0B",
        "or bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr w26, w5, w7",
        "bfxil x5, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "db 0x0B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x0B",
        "or ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr w5, w5, w7",
        "mov x26, x5",
        "tst w5, w5"
      ]
    },
    "db 0x48, 0x0B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x0B",
        "or rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr x5, x5, x7",
        "mov x26, x5",
        "tst x5, x5"
      ]
    },
    "or al, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0C",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0x1",
        "bfxil x4, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "or ax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0x1",
        "bfxil x4, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "or eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr w4, w4, #0x1",
        "mov x26, x4",
        "tst w4, w4"
      ]
    },
    "or rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr x4, x4, #0x1",
        "mov x26, x4",
        "tst x4, x4"
      ]
    },
    "or al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0C",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0xff",
        "bfxil x4, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "or ax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0xffff",
        "bfxil x4, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "or eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "orr w4, w4, w20",
        "mov x26, x4",
        "tst w4, w4"
      ]
    },
    "or rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "orr x4, x4, x20",
        "mov x26, x4",
        "tst x4, x4"
      ]
    },
    "adc bl, cl": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x10",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "uxtb w20, w5",
        "adc w21, wzr, w20",
        "add w22, w7, w21",
        "uxtb w26, w22",
        "cmp w26, w21",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "eor w20, w7, w20",
        "eor w21, w26, w7",
        "bic w20, w21, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "adc bx, cx": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x11",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "uxth w20, w5",
        "adc w21, wzr, w20",
        "add w22, w7, w21",
        "uxth w26, w22",
        "cmp w26, w21",
        "cset x21, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "eor w20, w7, w20",
        "eor w21, w26, w7",
        "bic w20, w21, w20",
        "rmif x20, #15, #nzcV",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "adc ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x11",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "adcs w26, w7, w5",
        "mov x7, x26"
      ]
    },
    "adc rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x11",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "adcs x26, x7, x5",
        "mov x7, x26"
      ]
    },
    "db 0x12, 0xcb": {
      "ExpectedInstructionCount": 14,
      "Comment": [
        "0x12",
        "adc bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "uxtb w20, w7",
        "adc w21, wzr, w20",
        "add w22, w5, w21",
        "uxtb w26, w22",
        "cmp w26, w21",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "eor w20, w5, w20",
        "eor w21, w26, w5",
        "bic w20, w21, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x5, x26, #0, #8"
      ]
    },
    "db 0x66, 0x13, 0xcb": {
      "ExpectedInstructionCount": 14,
      "Comment": [
        "0x13",
        "adc bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "uxth w20, w7",
        "adc w21, wzr, w20",
        "add w22, w5, w21",
        "uxth w26, w22",
        "cmp w26, w21",
        "cset x21, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "eor w20, w5, w20",
        "eor w21, w26, w5",
        "bic w20, w21, w20",
        "rmif x20, #15, #nzcV",
        "bfxil x5, x26, #0, #16"
      ]
    },
    "db 0x13, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x13",
        "adc ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "adcs w26, w5, w7",
        "mov x5, x26"
      ]
    },
    "db 0x48, 0x13, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x13",
        "adc rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "adcs x26, x5, x7",
        "mov x5, x26"
      ]
    },
    "adc al, 1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x14",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "mov w20, #0x1",
        "adc w20, wzr, w20",
        "add w21, w4, w20",
        "uxtb w26, w21",
        "cmp w26, w20",
        "cset x20, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x20, #63, #nzCv",
        "eor w20, w4, #0x1",
        "eor w21, w26, w4",
        "bic w20, w21, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "adc ax, 1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "mov w20, #0x1",
        "adc w20, wzr, w20",
        "add w21, w4, w20",
        "uxth w26, w21",
        "cmp w26, w20",
        "cset x20, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "eor w20, w4, #0x1",
        "eor w21, w26, w4",
        "bic w20, w21, w20",
        "rmif x20, #15, #nzcV",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "adc eax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "adcs w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "adc rax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "adcs x26, x4, x20",
        "mov x4, x26"
      ]
    },
    "adc al, -1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x14",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "mov w20, #0xff",
        "adc w20, wzr, w20",
        "add w21, w4, w20",
        "uxtb w26, w21",
        "cmp w26, w20",
        "cset x20, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x20, #63, #nzCv",
        "eor w20, w4, #0xff",
        "eor w21, w26, w4",
        "bic w20, w21, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "adc ax, -1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "mov w20, #0xffff",
        "adc w20, wzr, w20",
        "add w21, w4, w20",
        "uxth w26, w21",
        "cmp w26, w20",
        "cset x20, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "eor w20, w4, #0xffff",
        "eor w21, w26, w4",
        "bic w20, w21, w20",
        "rmif x20, #15, #nzcV",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "adc eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "adcs w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "adc rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "mvn w27, w4",
        "adcs x26, x4, x20",
        "mov x4, x26"
      ]
    },
    "sbb bl, cl": {
      "ExpectedInstructionCount": 15,
      "Comment": "0x18",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "uxtb w20, w7",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, w5",
        "uxtb w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "eor w21, w20, w5",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #7, #nzcV",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "sbb bx, cx": {
      "ExpectedInstructionCount": 15,
      "Comment": "0x19",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "uxth w20, w7",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, w5",
        "uxth w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "eor w21, w20, w5",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #15, #nzcV",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "sbb ebx, ecx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x19",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "cfinv",
        "sbcs w26, w7, w5",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "sbb rbx, rcx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x19",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "cfinv",
        "sbcs x26, x7, x5",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "db 0x1A, 0xcb": {
      "ExpectedInstructionCount": 15,
      "Comment": [
        "0x1A",
        "sbb bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "uxtb w20, w5",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, w7",
        "uxtb w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "eor w21, w20, w7",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #7, #nzcV",
        "bfxil x5, x26, #0, #8"
      ]
    },
    "db 0x66, 0x1B, 0xcb": {
      "ExpectedInstructionCount": 15,
      "Comment": [
        "0x1B",
        "sbb bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "uxth w20, w5",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, w7",
        "uxth w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "eor w21, w20, w7",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #15, #nzcV",
        "bfxil x5, x26, #0, #16"
      ]
    },
    "db 0x1B, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x1B",
        "sbb ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "cfinv",
        "sbcs w26, w5, w7",
        "cfinv",
        "mov x5, x26"
      ]
    },
    "db 0x48, 0x1B, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x1B",
        "sbb rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "cfinv",
        "sbcs x26, x5, x7",
        "cfinv",
        "mov x5, x26"
      ]
    },
    "sbb al, 1": {
      "ExpectedInstructionCount": 13,
      "Comment": "0x1C",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "uxtb w20, w4",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, #0x1 (1)",
        "uxtb w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "bic w20, w20, w26",
        "rmif x20, #7, #nzcV",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sbb ax, 1": {
      "ExpectedInstructionCount": 13,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "uxth w20, w4",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, #0x1 (1)",
        "uxth w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "bic w20, w20, w26",
        "rmif x20, #15, #nzcV",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sbb eax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "cfinv",
        "sbcs w26, w4, w20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sbb rax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "cfinv",
        "sbcs x26, x4, x20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sbb al, -1": {
      "ExpectedInstructionCount": 13,
      "Comment": "0x1C",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "uxtb w20, w4",
        "cset w21, hs",
        "sub w21, w20, w21",
        "sub w22, w21, #0xff (255)",
        "uxtb w26, w22",
        "cmp w21, w26",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "bic w20, w26, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sbb ax, -1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "uxth w21, w4",
        "cset w22, hs",
        "sub w22, w21, w22",
        "sub w20, w22, w20",
        "uxth w26, w20",
        "cmp w22, w26",
        "cset x20, lo",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "bic w20, w26, w21",
        "rmif x20, #15, #nzcV",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sbb eax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "cfinv",
        "sbcs w26, w4, w20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sbb rax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "mvn w27, w4",
        "cfinv",
        "sbcs x26, x4, x20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "and bl, cl": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x20",
      "ExpectedArm64ASM": [
        "and w26, w7, w5",
        "cmn wzr, w26, lsl #24",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "and bx, cx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x21",
      "ExpectedArm64ASM": [
        "and w26, w7, w5",
        "cmn wzr, w26, lsl #16",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "and ebx, ecx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x21",
      "ExpectedArm64ASM": [
        "ands w26, w7, w5",
        "mov x7, x26"
      ]
    },
    "and rbx, rcx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x21",
      "ExpectedArm64ASM": [
        "ands x26, x7, x5",
        "mov x7, x26"
      ]
    },
    "db 0x22, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x22",
        "and bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "and w26, w5, w7",
        "cmn wzr, w26, lsl #24",
        "bfxil x5, x26, #0, #8"
      ]
    },
    "db 0x66, 0x23, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x23",
        "and bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "and w26, w5, w7",
        "cmn wzr, w26, lsl #16",
        "bfxil x5, x26, #0, #16"
      ]
    },
    "db 0x23, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x23",
        "and ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "ands w26, w5, w7",
        "mov x5, x26"
      ]
    },
    "db 0x48, 0x23, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x23",
        "and rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "ands x26, x5, x7",
        "mov x5, x26"
      ]
    },
    "and al, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x24",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "and ax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmn wzr, w26, lsl #16",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "and eax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0x1",
        "mov x4, x26"
      ]
    },
    "and rax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0x1",
        "mov x4, x26"
      ]
    },
    "and al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x24",
      "ExpectedArm64ASM": [
        "and w26, w4, #0xff",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "and ax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "and w26, w4, #0xffff",
        "cmn wzr, w26, lsl #16",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "and eax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "ands w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "and rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "ands x26, x4, x20",
        "mov x4, x26"
      ]
    },
    "sub bl, cl": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x28",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "lsl w0, w7, #24",
        "cmp w0, w5, lsl #24",
        "sub w26, w7, w5",
        "cfinv",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "sub bx, cx": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x29",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "lsl w0, w7, #16",
        "cmp w0, w5, lsl #16",
        "sub w26, w7, w5",
        "cfinv",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "sub ebx, ecx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x29",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "subs w26, w7, w5",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "sub rbx, rcx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x29",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "subs x26, x7, x5",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "db 0x2A, 0xcb": {
      "ExpectedInstructionCount": 6,
      "Comment": [
        "0x2A",
        "sub bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "lsl w0, w5, #24",
        "cmp w0, w7, lsl #24",
        "sub w26, w5, w7",
        "cfinv",
        "bfxil x5, x26, #0, #8"
      ]
    },
    "db 0x66, 0x2B, 0xcb": {
      "ExpectedInstructionCount": 6,
      "Comment": [
        "0x2B",
        "sub bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "lsl w0, w5, #16",
        "cmp w0, w7, lsl #16",
        "sub w26, w5, w7",
        "cfinv",
        "bfxil x5, x26, #0, #16"
      ]
    },
    "db 0x2B, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x2B",
        "sub ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "subs w26, w5, w7",
        "cfinv",
        "mov x5, x26"
      ]
    },
    "db 0x48, 0x2B, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x2B",
        "sub rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "subs x26, x5, x7",
        "cfinv",
        "mov x5, x26"
      ]
    },
    "sub al, 1": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x2C",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0x1 (1)",
        "cfinv",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sub ax, 1": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, #0x1 (1)",
        "cfinv",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sub eax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "subs w26, w4, #0x1 (1)",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sub rax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "subs x26, x4, #0x1 (1)",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sub al, -1": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x2C",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0xff (255)",
        "cfinv",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sub ax, -1": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sub eax, -1": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "subs w26, w4, w20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sub rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds x26, x4, #0x1 (1)",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "xor bl, cl": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x30",
      "ExpectedArm64ASM": [
        "eor w26, w7, w5",
        "bfxil x7, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "xor bx, cx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x31",
      "ExpectedArm64ASM": [
        "eor w26, w7, w5",
        "bfxil x7, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "xor ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x31",
      "ExpectedArm64ASM": [
        "eor w7, w7, w5",
        "mov x26, x7",
        "tst w7, w7"
      ]
    },
    "xor rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x31",
      "ExpectedArm64ASM": [
        "eor x7, x7, x5",
        "mov x26, x7",
        "tst x7, x7"
      ]
    },
    "db 0x32, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x32",
        "xor bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w26, w5, w7",
        "bfxil x5, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "db 0x66, 0x33, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x33",
        "xor bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w26, w5, w7",
        "bfxil x5, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "db 0x33, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x33",
        "xor ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w5, w5, w7",
        "mov x26, x5",
        "tst w5, w5"
      ]
    },
    "db 0x48, 0x33, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x33",
        "xor rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x5, x5, x7",
        "mov x26, x5",
        "tst x5, x5"
      ]
    },
    "xor al, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x34",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0x1",
        "bfxil x4, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "xor ax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0x1",
        "bfxil x4, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "xor eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor w4, w4, #0x1",
        "mov x26, x4",
        "tst w4, w4"
      ]
    },
    "xor rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor x4, x4, #0x1",
        "mov x26, x4",
        "tst x4, x4"
      ]
    },
    "cmp bl, cl": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x38",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "lsl w0, w7, #24",
        "cmp w0, w5, lsl #24",
        "sub w26, w7, w5",
        "cfinv"
      ]
    },
    "xor al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x34",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0xff",
        "bfxil x4, x26, #0, #8",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "xor ax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0xffff",
        "bfxil x4, x26, #0, #16",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "xor eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "eor w4, w4, w20",
        "mov x26, x4",
        "tst w4, w4"
      ]
    },
    "xor rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "eor x4, x4, x20",
        "mov x26, x4",
        "tst x4, x4"
      ]
    },
    "cmp bx, cx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x39",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "lsl w0, w7, #16",
        "cmp w0, w5, lsl #16",
        "sub w26, w7, w5",
        "cfinv"
      ]
    },
    "cmp ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x39",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "subs w26, w7, w5",
        "cfinv"
      ]
    },
    "cmp rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x39",
      "ExpectedArm64ASM": [
        "eor w27, w7, w5",
        "subs x26, x7, x5",
        "cfinv"
      ]
    },
    "db 0x3A, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x3A",
        "cmp bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "lsl w0, w5, #24",
        "cmp w0, w7, lsl #24",
        "sub w26, w5, w7",
        "cfinv"
      ]
    },
    "db 0x66, 0x3B, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x3B",
        "cmp bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "lsl w0, w5, #16",
        "cmp w0, w7, lsl #16",
        "sub w26, w5, w7",
        "cfinv"
      ]
    },
    "db 0x3B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x3B",
        "cmp ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "subs w26, w5, w7",
        "cfinv"
      ]
    },
    "db 0x48, 0x3B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x3B",
        "cmp rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w27, w5, w7",
        "subs x26, x5, x7",
        "cfinv"
      ]
    },
    "cmp al, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x3C",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0x1 (1)",
        "cfinv"
      ]
    },
    "cmp ax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mov x27, x4",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, #0x1 (1)",
        "cfinv"
      ]
    },
    "cmp eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "subs w26, w4, #0x1 (1)",
        "cfinv"
      ]
    },
    "cmp rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov x27, x4",
        "subs x26, x4, #0x1 (1)",
        "cfinv"
      ]
    },
    "cmp al, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x3C",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0xff (255)",
        "cfinv"
      ]
    },
    "cmp ax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv"
      ]
    },
    "cmp eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "subs w26, w4, w20",
        "cfinv"
      ]
    },
    "cmp rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds x26, x4, #0x1 (1)",
        "cfinv"
      ]
    },
    "imul ax, bx, 257": {
      "ExpectedInstructionCount": 8,
      "Comment": "0x69",
      "ExpectedArm64ASM": [
        "sxth x20, w7",
        "mov w21, #0x101",
        "mul x20, x20, x21",
        "sbfx x21, x20, #16, #16",
        "bfxil x4, x20, #0, #16",
        "sbfx x20, x20, #15, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul eax, ebx, 257": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x69",
      "ExpectedArm64ASM": [
        "mov w20, #0x101",
        "smull x21, w7, w20",
        "asr x21, x21, #32",
        "mul w4, w7, w20",
        "sbfx x20, x4, #31, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul rax, rbx, 257": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x69",
      "ExpectedArm64ASM": [
        "mov w20, #0x101",
        "smulh x21, x7, x20",
        "mul x4, x7, x20",
        "asr x20, x4, #63",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul ax, bx, 3": {
      "ExpectedInstructionCount": 8,
      "Comment": "0x6b",
      "ExpectedArm64ASM": [
        "sxth x20, w7",
        "mov w21, #0x3",
        "mul x20, x20, x21",
        "sbfx x21, x20, #16, #16",
        "bfxil x4, x20, #0, #16",
        "sbfx x20, x20, #15, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul eax, ebx, 3": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x6b",
      "ExpectedArm64ASM": [
        "mov w20, #0x3",
        "smull x21, w7, w20",
        "asr x21, x21, #32",
        "mul w4, w7, w20",
        "sbfx x20, x4, #31, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul rax, rbx, 3": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x6b",
      "ExpectedArm64ASM": [
        "mov w20, #0x3",
        "smulh x21, x7, x20",
        "mul x4, x7, x20",
        "asr x20, x4, #63",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "test al, bl": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "and w26, w4, w7",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "test ax, bx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "and w26, w4, w7",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "test eax, ebx": {
      "ExpectedInstructionCount": 1,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "ands w26, w4, w7"
      ]
    },
    "test rax, rbx": {
      "ExpectedInstructionCount": 1,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "ands x26, x4, x7"
      ]
    },
    "pushf": {
      "ExpectedInstructionCount": 39,
      "Comment": "0x9c",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "eor w21, w27, w26",
        "ubfx w21, w21, #4, #1",
        "orr x20, x20, x21, lsl #4",
        "ldrb w21, [x28, #984]",
        "orr x20, x20, x21, lsl #8",
        "ldrb w21, [x28, #985]",
        "orr x20, x20, x21, lsl #9",
        "ldrsb x21, [x28, #986]",
        "lsr x21, x21, #63",
        "orr x20, x20, x21, lsl #10",
        "cset w21, vs",
        "orr x20, x20, x21, lsl #11",
        "ldrb w21, [x28, #988]",
        "orr x20, x20, x21, lsl #12",
        "ldrb w21, [x28, #990]",
        "orr x20, x20, x21, lsl #14",
        "ldrb w21, [x28, #992]",
        "orr x20, x20, x21, lsl #16",
        "ldrb w21, [x28, #993]",
        "orr x20, x20, x21, lsl #17",
        "ldrb w21, [x28, #994]",
        "orr x20, x20, x21, lsl #18",
        "ldrb w21, [x28, #995]",
        "orr x20, x20, x21, lsl #19",
        "ldrb w21, [x28, #996]",
        "orr x20, x20, x21, lsl #20",
        "ldrb w21, [x28, #997]",
        "orr x20, x20, x21, lsl #21",
        "eor w21, w26, w26, lsr #4",
        "eor w21, w21, w21, lsr #2",
        "eor w21, w21, w21, lsr #1",
        "orr x21, x21, #0xfffffffffffffffe",
        "orn x20, x20, x21, ror #62",
        "mrs x21, nzcv",
        "and x21, x21, #0xc0000000",
        "orr x20, x20, x21, lsr #24",
        "orr x20, x20, #0x2",
        "str x20, [x8, #-8]!"
      ]
    },
    "pushfq": {
      "ExpectedInstructionCount": 39,
      "Comment": "0x9c",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "eor w21, w27, w26",
        "ubfx w21, w21, #4, #1",
        "orr x20, x20, x21, lsl #4",
        "ldrb w21, [x28, #984]",
        "orr x20, x20, x21, lsl #8",
        "ldrb w21, [x28, #985]",
        "orr x20, x20, x21, lsl #9",
        "ldrsb x21, [x28, #986]",
        "lsr x21, x21, #63",
        "orr x20, x20, x21, lsl #10",
        "cset w21, vs",
        "orr x20, x20, x21, lsl #11",
        "ldrb w21, [x28, #988]",
        "orr x20, x20, x21, lsl #12",
        "ldrb w21, [x28, #990]",
        "orr x20, x20, x21, lsl #14",
        "ldrb w21, [x28, #992]",
        "orr x20, x20, x21, lsl #16",
        "ldrb w21, [x28, #993]",
        "orr x20, x20, x21, lsl #17",
        "ldrb w21, [x28, #994]",
        "orr x20, x20, x21, lsl #18",
        "ldrb w21, [x28, #995]",
        "orr x20, x20, x21, lsl #19",
        "ldrb w21, [x28, #996]",
        "orr x20, x20, x21, lsl #20",
        "ldrb w21, [x28, #997]",
        "orr x20, x20, x21, lsl #21",
        "eor w21, w26, w26, lsr #4",
        "eor w21, w21, w21, lsr #2",
        "eor w21, w21, w21, lsr #1",
        "orr x21, x21, #0xfffffffffffffffe",
        "orn x20, x20, x21, ror #62",
        "mrs x21, nzcv",
        "and x21, x21, #0xc0000000",
        "orr x20, x20, x21, lsr #24",
        "orr x20, x20, #0x2",
        "str x20, [x8, #-8]!"
      ]
    },
    "popf": {
      "ExpectedInstructionCount": 34,
      "Comment": "0x9d",
      "ExpectedArm64ASM": [
        "ldr x20, [x8]",
        "add x8, x8, #0x8 (8)",
        "mov w21, #0x202",
        "orr x27, x20, x21",
        "rmif x27, #63, #nzCv",
        "ubfx w20, w27, #2, #1",
        "mov w21, #0x1",
        "eor w26, w20, #0x1",
        "rmif x27, #4, #nZcv",
        "rmif x27, #4, #Nzcv",
        "ubfx w20, w27, #8, #1",
        "strb w20, [x28, #984]",
        "ubfx w20, w27, #9, #1",
        "strb w20, [x28, #985]",
        "ubfx w20, w27, #10, #1",
        "sub x20, x21, x20, lsl #1",
        "strb w20, [x28, #986]",
        "rmif x27, #11, #nzcV",
        "ubfx w20, w27, #12, #1",
        "strb w20, [x28, #988]",
        "ubfx w20, w27, #14, #1",
        "strb w20, [x28, #990]",
        "ubfx w20, w27, #16, #1",
        "strb w20, [x28, #992]",
        "ubfx w20, w27, #17, #1",
        "strb w20, [x28, #993]",
        "ubfx w20, w27, #18, #1",
        "strb w20, [x28, #994]",
        "ubfx w20, w27, #19, #1",
        "strb w20, [x28, #995]",
        "ubfx w20, w27, #20, #1",
        "strb w20, [x28, #996]",
        "ubfx w20, w27, #21, #1",
        "strb w20, [x28, #997]"
      ]
    },
    "sahf": {
      "ExpectedInstructionCount": 9,
      "Comment": "0x9e",
      "ExpectedArm64ASM": [
        "ubfx w20, w4, #8, #8",
        "mov w21, #0x28",
        "bic x20, x20, x21",
        "orr x27, x20, #0x2",
        "rmif x27, #63, #nzCv",
        "ubfx w20, w27, #2, #1",
        "eor w26, w20, #0x1",
        "rmif x27, #4, #nZcv",
        "rmif x27, #4, #Nzcv"
      ]
    },
    "lahf": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x9f",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "eor w21, w27, w26",
        "ubfx w21, w21, #4, #1",
        "orr x20, x20, x21, lsl #4",
        "eor w21, w26, w26, lsr #4",
        "eor w21, w21, w21, lsr #2",
        "eor w21, w21, w21, lsr #1",
        "orr x21, x21, #0xfffffffffffffffe",
        "orn x20, x20, x21, ror #62",
        "mrs x21, nzcv",
        "and x21, x21, #0xc0000000",
        "orr x20, x20, x21, lsr #24",
        "orr x20, x20, #0x2",
        "bfi x4, x20, #8, #8"
      ]
    },
    "cmpsb": {
      "ExpectedInstructionCount": 10,
      "Comment": [
        "0xa6"
      ],
      "ExpectedArm64ASM": [
        "ldrb w20, [x11]",
        "ldrb w21, [x10]",
        "ldrsb x22, [x28, #986]",
        "add x11, x11, x22",
        "add x10, x10, x22",
        "eor w27, w21, w20",
        "lsl w0, w21, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w21, w20",
        "cfinv"
      ]
    },
    "cmpsw": {
      "ExpectedInstructionCount": 11,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldrh w20, [x11]",
        "ldrh w21, [x10]",
        "ldrsb x22, [x28, #986]",
        "lsl x22, x22, #1",
        "add x11, x11, x22",
        "add x10, x10, x22",
        "eor w27, w21, w20",
        "lsl w0, w21, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w21, w20",
        "cfinv"
      ]
    },
    "cmpsd": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldr w20, [x11]",
        "ldr w21, [x10]",
        "ldrsb x22, [x28, #986]",
        "lsl x22, x22, #2",
        "add x11, x11, x22",
        "add x10, x10, x22",
        "eor w27, w21, w20",
        "subs w26, w21, w20",
        "cfinv"
      ]
    },
    "cmpsq": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldr x20, [x11]",
        "ldr x21, [x10]",
        "ldrsb x22, [x28, #986]",
        "lsl x22, x22, #3",
        "add x11, x11, x22",
        "add x10, x10, x22",
        "eor w27, w21, w20",
        "subs x26, x21, x20",
        "cfinv"
      ]
    },
    "repz cmpsb": {
      "ExpectedInstructionCount": 27,
      "Comment": "0xa6",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x6c",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "lsl w0, w21, #24",
        "cmp w0, w26, lsl #24",
        "sub w26, w21, w26",
        "cfinv"
      ]
    },
    "repz cmpsw": {
      "ExpectedInstructionCount": 27,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x6c",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "add x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "sub x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "lsl w0, w21, #16",
        "cmp w0, w26, lsl #16",
        "sub w26, w21, w26",
        "cfinv"
      ]
    },
    "repz cmpsd": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x64",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "add x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "sub x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "subs w26, w21, w26",
        "cfinv"
      ]
    },
    "repz cmpsq": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x64",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "add x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "sub x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "subs x26, x21, x26",
        "cfinv"
      ]
    },
    "repnz cmpsb": {
      "ExpectedInstructionCount": 27,
      "Comment": "0xa6",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x6c",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "lsl w0, w21, #24",
        "cmp w0, w26, lsl #24",
        "sub w26, w21, w26",
        "cfinv"
      ]
    },
    "repnz cmpsw": {
      "ExpectedInstructionCount": 27,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x6c",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "add x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "sub x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "lsl w0, w21, #16",
        "cmp w0, w26, lsl #16",
        "sub w26, w21, w26",
        "cfinv"
      ]
    },
    "repnz cmpsd": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x64",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "add x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "sub x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "subs w26, w21, w26",
        "cfinv"
      ]
    },
    "repnz cmpsq": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x5, #+0x64",
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "add x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x5, x5, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "sub x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor w20, w27, w26",
        "mov x21, x27",
        "mov x27, x20",
        "subs x26, x21, x26",
        "cfinv"
      ]
    },
    "test al, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa8",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "test ax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "test eax, 1": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0x1"
      ]
    },
    "test rax, 1": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0x1"
      ]
    },
    "test al, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa8",
      "ExpectedArm64ASM": [
        "mov x26, x4",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "test ax, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "mov x26, x4",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "test eax, -1": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "ands w26, w4, w4"
      ]
    },
    "test rax, -1": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "ands x26, x4, x4"
      ]
    },
    "scasb": {
      "ExpectedInstructionCount": 8,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrb w20, [x11]",
        "ldrsb x21, [x28, #986]",
        "add x11, x11, x21",
        "eor w27, w4, w20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "cfinv"
      ]
    },
    "scasw": {
      "ExpectedInstructionCount": 8,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrh w20, [x11]",
        "ldrsb x21, [x28, #986]",
        "add x11, x11, x21, lsl #1",
        "eor w27, w4, w20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv"
      ]
    },
    "scasd": {
      "ExpectedInstructionCount": 6,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldr w20, [x11]",
        "ldrsb x21, [x28, #986]",
        "add x11, x11, x21, lsl #2",
        "eor w27, w4, w20",
        "subs w26, w4, w20",
        "cfinv"
      ]
    },
    "scasq": {
      "ExpectedInstructionCount": 6,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldr x20, [x11]",
        "ldrsb x21, [x28, #986]",
        "add x11, x11, x21, lsl #3",
        "eor w27, w4, w20",
        "subs x26, x4, x20",
        "cfinv"
      ]
    },
    "repz scasb": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x30",
        "cbz x5, #+0x28",
        "ldrb w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "b.eq #-0x24",
        "b #+0x2c",
        "cbz x5, #+0x28",
        "ldrb w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "b.eq #-0x24"
      ]
    },
    "repz scasw": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x30",
        "cbz x5, #+0x28",
        "ldrh w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "b.eq #-0x24",
        "b #+0x2c",
        "cbz x5, #+0x28",
        "ldrh w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "b.eq #-0x24"
      ]
    },
    "repz scasd": {
      "ExpectedInstructionCount": 21,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x28",
        "cbz x5, #+0x20",
        "ldr w20, [x11]",
        "eor w27, w4, w20",
        "subs w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "b.eq #-0x1c",
        "b #+0x24",
        "cbz x5, #+0x20",
        "ldr w20, [x11]",
        "eor w27, w4, w20",
        "subs w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "b.eq #-0x1c"
      ]
    },
    "repz scasq": {
      "ExpectedInstructionCount": 21,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x28",
        "cbz x5, #+0x20",
        "ldr x20, [x11]",
        "eor w27, w4, w20",
        "subs x26, x4, x20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "b.eq #-0x1c",
        "b #+0x24",
        "cbz x5, #+0x20",
        "ldr x20, [x11]",
        "eor w27, w4, w20",
        "subs x26, x4, x20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "b.eq #-0x1c"
      ]
    },
    "repnz scasb": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x30",
        "cbz x5, #+0x28",
        "ldrb w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "b.ne #-0x24",
        "b #+0x2c",
        "cbz x5, #+0x28",
        "ldrb w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "b.ne #-0x24"
      ]
    },
    "repnz scasw": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x30",
        "cbz x5, #+0x28",
        "ldrh w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "b.ne #-0x24",
        "b #+0x2c",
        "cbz x5, #+0x28",
        "ldrh w20, [x11]",
        "eor w27, w4, w20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "b.ne #-0x24"
      ]
    },
    "repnz scasd": {
      "ExpectedInstructionCount": 21,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x28",
        "cbz x5, #+0x20",
        "ldr w20, [x11]",
        "eor w27, w4, w20",
        "subs w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "b.ne #-0x1c",
        "b #+0x24",
        "cbz x5, #+0x20",
        "ldr w20, [x11]",
        "eor w27, w4, w20",
        "subs w26, w4, w20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "b.ne #-0x1c"
      ]
    },
    "repnz scasq": {
      "ExpectedInstructionCount": 21,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #986]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x28",
        "cbz x5, #+0x20",
        "ldr x20, [x11]",
        "eor w27, w4, w20",
        "subs x26, x4, x20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "b.ne #-0x1c",
        "b #+0x24",
        "cbz x5, #+0x20",
        "ldr x20, [x11]",
        "eor w27, w4, w20",
        "subs x26, x4, x20",
        "cfinv",
        "sub x5, x5, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "b.ne #-0x1c"
      ]
    },
    "cmc": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xf5",
      "ExpectedArm64ASM": [
        "cfinv"
      ]
    },
    "clc": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xf8",
      "ExpectedArm64ASM": [
        "rmif xzr, #63, #nzCv"
      ]
    },
    "stc": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xf9",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "rmif x20, #63, #nzCv"
      ]
    }
  }
}