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FEX-Emu--FEX/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
T
Alyssa Rosenzweig 27c8bf3021 InstCountCI: explicitly disable AFP everywhere 
(except for when we explicitly enable AFP).

Since AFP gets saved/restored, we get `msr fpcr` garbage in random instructions
when AFP is enabled. Explicitly disable everywhere since it's not worth our time
to triage which files might hit that path. Fixes instcountci on AFP-supporting
hosts now that we have AFP enabled.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-06-18 11:40:20 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"FLAGM",
"FLAGM2"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP"
]
},
"Instructions": {
"add al, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #8"
]
},
"or al, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24"
]
},
"adc al, 1": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
"uxtb w26, w21",
"cmp w26, w20",
"cset x20, lo",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0x1",
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, #0x1 (1)",
"uxtb w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"and al, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"and w26, w4, #0x1",
"cmn wzr, w26, lsl #24",
"bfxil x4, x26, #0, #8"
]
},
"sub al, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"bfxil x4, x26, #0, #8"
]
},
"xor al, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24"
]
},
"cmp al, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv"
]
},
"add al, -1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0xff (255)",
"bfxil x4, x26, #0, #8"
]
},
"or al, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0xff",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24"
]
},
"adc al, -1": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mvn w27, w4",
"mov w20, #0xff",
"adc w20, wzr, w20",
"add w21, w4, w20",
"uxtb w26, w21",
"cmp w26, w20",
"cset x20, lo",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0xff",
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mvn w27, w4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, #0xff (255)",
"uxtb w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"bic w20, w26, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"and al, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"and w26, w4, #0xff",
"cmn wzr, w26, lsl #24",
"bfxil x4, x26, #0, #8"
]
},
"sub al, -1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0xff (255)",
"cfinv",
"bfxil x4, x26, #0, #8"
]
},
"xor al, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0xff",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24"
]
},
"cmp al, -1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w27, w4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0xff (255)",
"cfinv"
]
},
"add ax, 256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x100 (256)",
"bfxil x4, x26, #0, #16"
]
},
"add eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x100 (256)",
"mov x4, x26"
]
},
"add rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mov x4, x26"
]
},
"or eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, 256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
"adc rax, 256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
"sbb eax, 256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, 256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, 256": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"ands w26, w4, #0x100",
"mov x4, x26"
]
},
"and rax, 256": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"ands x26, x4, #0x100",
"mov x4, x26"
]
},
"sub eax, 256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"cfinv",
"mov x4, x26"
]
},
"sub rax, 256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"cfinv",
"mov x4, x26"
]
},
"xor eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"cfinv"
]
},
"cmp rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"cfinv"
]
},
"add ax, -256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff00",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, w20",
"bfxil x4, x26, #0, #16"
]
},
"add eax, -256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"adds w26, w4, w20",
"mov x4, x26"
]
},
"add rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mov x4, x26"
]
},
"or eax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, -256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
"adc rax, -256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
"sbb eax, -256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, -256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, -256": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"ands w26, w4, #0xffffff00",
"mov x4, x26"
]
},
"and rax, -256": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"ands x26, x4, #0xffffffffffffff00",
"mov x4, x26"
]
},
"sub eax, -256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sub rax, -256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"cfinv",
"mov x4, x26"
]
},
"xor eax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, -256": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"cfinv"
]
},
"cmp rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"cfinv"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #16"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x4, x26"
]
},
"add rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x4, x26"
]
},
"or eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
"adc rax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
"sbb eax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, 1": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"ands w26, w4, #0x1",
"mov x4, x26"
]
},
"and rax, 1": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"ands x26, x4, #0x1",
"mov x4, x26"
]
},
"sub eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x4, x26"
]
},
"sub rax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x4, x26"
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv"
]
},
"add ax, -1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"mvn w27, w4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, w20",
"bfxil x4, x26, #0, #16"
]
},
"add eax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w27, w4",
"adds w26, w4, w20",
"mov x4, x26"
]
},
"add rax, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mvn w27, w4",
"subs x26, x4, #0x1 (1)",
"mov x4, x26"
]
},
"or eax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w27, w4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
"adc rax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mvn w27, w4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
"sbb eax, -1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w27, w4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sbb rax, -1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mvn w27, w4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x4, x26"
]
},
"and eax, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ands w26, w4, w20",
"mov x4, x26"
]
},
"and rax, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ands x26, x4, x20",
"mov x4, x26"
]
},
"sub eax, -1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w27, w4",
"subs w26, w4, w20",
"cfinv",
"mov x4, x26"
]
},
"sub rax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mvn w27, w4",
"adds x26, x4, #0x1 (1)",
"cfinv",
"mov x4, x26"
]
},
"xor eax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, -1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w27, w4",
"subs w26, w4, w20",
"cfinv"
]
},
"cmp rax, -1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mvn w27, w4",
"adds x26, x4, #0x1 (1)",
"cfinv"
]
},
"rol al, 2": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xC0 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"ror w20, w20, #30",
"bfxil x4, x20, #0, #8",
"rmif x20, #63, #nzCv"
]
},
"ror al, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC0 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #8, #8",
"ror w20, w20, #2",
"bfxil x4, x20, #0, #8",
"rmif x20, #6, #nzCv"
]
},
"rcl al, 2": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP2 0xC0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x0",
"cset w22, hs",
"bfi x21, x20, #55, #8",
"bfi x21, x22, #63, #1",
"bfi x21, x20, #46, #8",
"bfi x21, x22, #54, #1",
"bfi x21, x20, #37, #8",
"bfi x21, x22, #45, #1",
"bfi x21, x20, #28, #8",
"bfi x21, x22, #36, #1",
"bfi x21, x20, #19, #8",
"bfi x21, x22, #27, #1",
"bfxil x21, x20, #0, #8",
"ror x20, x21, #62",
"bfxil x4, x20, #0, #8",
"ror x20, x21, #61",
"rmif x20, #63, #nzCv"
]
},
"rcr al, 2": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xC0 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"uxtb w21, w4",
"bfi x21, x20, #8, #1",
"bfi x21, x21, #9, #9",
"bfi x21, x21, #18, #18",
"bfi x21, x21, #36, #9",
"lsr w20, w21, #2",
"bfxil x4, x20, #0, #8",
"rmif x21, #0, #nzCv"
]
},
"shl al, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC0 /4",
"ExpectedArm64ASM": [
"lsl w26, w4, #2",
"cmn wzr, w26, lsl #24",
"rmif x4, #5, #nzCv",
"bfxil x4, x26, #0, #8"
]
},
"shr al, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC0 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w26, w20, #2",
"cmn wzr, w26, lsl #24",
"rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #8"
]
},
"sar al, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC0 /7",
"ExpectedArm64ASM": [
"sxtb x20, w4",
"asr w26, w20, #2",
"cmn wzr, w26, lsl #24",
"rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #8"
]
},
"rol ax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, #30",
"bfxil x4, x20, #0, #16",
"rmif x20, #63, #nzCv"
]
},
"rol eax, 2": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xC1 /0",
"ExpectedArm64ASM": [
"ror w4, w4, #30",
"rmif x4, #63, #nzCv"
]
},
"rol rax, 2": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xC1 /0",
"ExpectedArm64ASM": [
"ror x4, x4, #62",
"rmif x4, #63, #nzCv"
]
},
"ror ax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, #2",
"bfxil x4, x20, #0, #16",
"rmif x20, #14, #nzCv"
]
},
"ror eax, 2": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xC1 /1",
"ExpectedArm64ASM": [
"ror w4, w4, #2",
"rmif x4, #30, #nzCv"
]
},
"ror rax, 2": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xC1 /1",
"ExpectedArm64ASM": [
"ror x4, x4, #2",
"rmif x4, #62, #nzCv"
]
},
"rcl ax, 2": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov w21, #0x0",
"cset w22, hs",
"bfi x21, x20, #47, #16",
"bfi x21, x22, #63, #1",
"bfi x21, x20, #30, #16",
"bfi x21, x22, #46, #1",
"bfi x21, x20, #13, #16",
"bfi x21, x22, #29, #1",
"bfxil x21, x20, #0, #16",
"ror x20, x21, #62",
"bfxil x4, x20, #0, #16",
"ror x20, x21, #61",
"rmif x20, #63, #nzCv"
]
},
"rcl eax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"lsl w20, w4, #2",
"cset w21, hs",
"orr w20, w20, w4, lsr #31",
"rmif x4, #29, #nzCv",
"orr w4, w20, w21, lsl #1"
]
},
"rcl rax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"lsl x20, x4, #2",
"cset w21, hs",
"orr x20, x20, x4, lsr #63",
"rmif x4, #61, #nzCv",
"orr x4, x20, x21, lsl #1"
]
},
"rcr ax, 2": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"uxth w21, w4",
"bfi x21, x20, #16, #1",
"bfi x21, x21, #17, #17",
"bfi x21, x21, #34, #17",
"lsr w20, w21, #2",
"bfxil x4, x20, #0, #16",
"rmif x21, #0, #nzCv"
]
},
"rcr eax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"lsr w20, w4, #2",
"cset w21, hs",
"orr w20, w20, w4, lsl #31",
"rmif x4, #0, #nzCv",
"orr w4, w20, w21, lsl #30"
]
},
"rcr rax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"lsr x20, x4, #2",
"cset w21, hs",
"orr x20, x20, x4, lsl #63",
"rmif x4, #0, #nzCv",
"orr x4, x20, x21, lsl #62"
]
},
"shl ax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"lsl w26, w4, #2",
"cmn wzr, w26, lsl #16",
"rmif x4, #13, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
"shl eax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"lsl w26, w4, #2",
"tst w26, w26",
"rmif x4, #29, #nzCv",
"mov x4, x26"
]
},
"shl rax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"lsl x26, x4, #2",
"tst x26, x26",
"rmif x4, #61, #nzCv",
"mov x4, x26"
]
},
"shr ax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w26, w20, #2",
"cmn wzr, w26, lsl #16",
"rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
"shr eax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"lsr w26, w4, #2",
"tst w26, w26",
"rmif x4, #0, #nzCv",
"mov x4, x26"
]
},
"shr rax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"lsr x26, x4, #2",
"tst x26, x26",
"rmif x4, #0, #nzCv",
"mov x4, x26"
]
},
"sar ax, 2": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [
"sxth x20, w4",
"asr w26, w20, #2",
"cmn wzr, w26, lsl #16",
"rmif x20, #0, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
"sar eax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [
"asr w26, w4, #2",
"tst w26, w26",
"rmif x4, #0, #nzCv",
"mov x4, x26"
]
},
"sar rax, 2": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /7",
"ExpectedArm64ASM": [
"asr x26, x4, #2",
"tst x26, x26",
"rmif x4, #0, #nzCv",
"mov x4, x26"
]
},
"rol al, 1": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd0 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"ror w20, w20, #31",
"bfxil x4, x20, #0, #8",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #7",
"rmif x20, #0, #nzcV"
]
},
"ror al, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd0 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #8, #8",
"ror w20, w20, #1",
"bfxil x4, x20, #0, #8",
"rmif x20, #6, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #6, #nzcV"
]
},
"rcl al, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"orr w21, w21, w20, lsl #1",
"rmif x20, #6, #nzCv",
"eor w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x21, #0, #8"
]
},
"rcr al, 1": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd0 /3",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"cset w21, hs",
"rmif x20, #63, #nzCv",
"ubfx w20, w20, #1, #7",
"bfi w20, w21, #7, #1",
"bfxil x4, x20, #0, #8",
"eor w20, w20, w20, lsr #1",
"rmif x20, #6, #nzcV"
]
},
"shl al, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd0 /4",
"ExpectedArm64ASM": [
"lsl w26, w4, #1",
"cmn wzr, w26, lsl #24",
"rmif x4, #6, #nzCv",
"eor w20, w26, w4",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"shr al, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd0 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w26, w20, #1",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sar al, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd0 /7",
"ExpectedArm64ASM": [
"sxtb x20, w4",
"asr w26, w20, #1",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"bfxil x4, x26, #0, #8"
]
},
"rol ax, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /0",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, #31",
"bfxil x4, x20, #0, #16",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #15",
"rmif x20, #0, #nzcV"
]
},
"rol eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /0",
"ExpectedArm64ASM": [
"ror w4, w4, #31",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #31",
"rmif x20, #0, #nzcV"
]
},
"rol rax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /0",
"ExpectedArm64ASM": [
"ror x4, x4, #63",
"rmif x4, #63, #nzCv",
"eor x20, x4, x4, lsr #63",
"rmif x20, #0, #nzcV"
]
},
"ror ax, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /1",
"ExpectedArm64ASM": [
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, #1",
"bfxil x4, x20, #0, #16",
"rmif x20, #14, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #14, #nzcV"
]
},
"ror eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /1",
"ExpectedArm64ASM": [
"ror w4, w4, #1",
"rmif x4, #30, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"ror rax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /1",
"ExpectedArm64ASM": [
"ror x4, x4, #1",
"rmif x4, #62, #nzCv",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
},
"rcl ax, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
"cset w21, hs",
"orr w21, w21, w20, lsl #1",
"rmif x20, #14, #nzCv",
"eor w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x4, x21, #0, #16"
]
},
"rcl eax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"mov w20, w4",
"cset w21, hs",
"orr w4, w21, w20, lsl #1",
"rmif x20, #30, #nzCv",
"eor w20, w4, w20",
"rmif x20, #31, #nzcV"
]
},
"rcl rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /2",
"ExpectedArm64ASM": [
"cset w20, hs",
"orr x20, x20, x4, lsl #1",
"rmif x4, #62, #nzCv",
"eor x21, x20, x4",
"rmif x21, #63, #nzcV",
"mov x4, x20"
]
},
"rcr ax, 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"rmif x4, #63, #nzCv",
"ubfx w21, w4, #1, #15",
"orr w20, w21, w20, lsl #15",
"bfxil x4, x20, #0, #16",
"eor x20, x20, x20, lsr #1",
"rmif x20, #14, #nzcV"
]
},
"rcr eax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"rmif x4, #63, #nzCv",
"extr w4, w20, w4, #1",
"eor x20, x4, x4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"rcr rax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"rmif x4, #63, #nzCv",
"extr x4, x20, x4, #1",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
},
"shl ax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"lsl w26, w4, #1",
"cmn wzr, w26, lsl #16",
"rmif x4, #14, #nzCv",
"eor w20, w26, w4",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"shl eax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"lsl w26, w4, #1",
"tst w26, w26",
"rmif x4, #30, #nzCv",
"eor w20, w26, w4",
"rmif x20, #31, #nzcV",
"mov x4, x26"
]
},
"shl rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"lsl x26, x4, #1",
"tst x26, x26",
"rmif x4, #62, #nzCv",
"eor x20, x26, x4",
"rmif x20, #63, #nzcV",
"mov x4, x26"
]
},
"shr ax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w26, w20, #1",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"shr eax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [
"lsr w26, w4, #1",
"tst w26, w26",
"rmif x4, #63, #nzCv",
"rmif x4, #31, #nzcV",
"mov x4, x26"
]
},
"shr rax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [
"lsr x26, x4, #1",
"tst x26, x26",
"rmif x4, #63, #nzCv",
"rmif x4, #63, #nzcV",
"mov x4, x26"
]
},
"sar ax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [
"sxth x20, w4",
"asr w26, w20, #1",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
"sar eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [
"asr w26, w4, #1",
"tst w26, w26",
"rmif x4, #63, #nzCv",
"mov x4, x26"
]
},
"sar rax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xd1 /7",
"ExpectedArm64ASM": [
"asr x26, x4, #1",
"tst x26, x26",
"rmif x4, #63, #nzCv",
"mov x4, x26"
]
},
"rol al, cl": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x28",
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"neg w21, w5",
"ror w20, w20, w21",
"bfxil x4, x20, #0, #8",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #7",
"rmif x20, #0, #nzcV"
]
},
"ror al, cl": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd2 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x24",
"mov w20, w4",
"bfi w20, w4, #8, #8",
"bfi w20, w20, #16, #16",
"ror w20, w20, w5",
"bfxil x4, x20, #0, #8",
"rmif x20, #6, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #6, #nzcV"
]
},
"rcl al, cl": {
"ExpectedInstructionCount": 26,
"Comment": "GROUP2 0xd2 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x64",
"and w20, w5, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, hs",
"bfi x22, x21, #55, #8",
"bfi x22, x23, #63, #1",
"bfi x22, x21, #46, #8",
"bfi x22, x23, #54, #1",
"bfi x22, x21, #37, #8",
"bfi x22, x23, #45, #1",
"bfi x22, x21, #28, #8",
"bfi x22, x23, #36, #1",
"bfi x22, x21, #19, #8",
"bfi x22, x23, #27, #1",
"bfxil x22, x21, #0, #8",
"neg w21, w20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #8",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x22, x20",
"rmif x20, #63, #nzCv",
"eor x20, x20, x21, lsr #7",
"rmif x20, #0, #nzcV"
]
},
"rcr al, cl": {
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd2 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x38",
"cset w20, hs",
"uxtb w21, w4",
"bfi x21, x20, #8, #1",
"bfi x21, x21, #9, #9",
"bfi x21, x21, #18, #18",
"bfi x21, x21, #36, #9",
"lsr w20, w21, w5",
"bfxil x4, x20, #0, #8",
"sub w22, w5, #0x1 (1)",
"lsr w21, w21, w22",
"rmif x21, #63, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #6, #nzcV"
]
},
"shl al, cl": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"cbz w5, #+0x24",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
"mov w0, #0x8",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV",
"bfxil x4, x20, #0, #8"
]
},
"shr al, cl": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w21, w20, w5",
"cbz w5, #+0x20",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w21",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV",
"bfxil x4, x21, #0, #8"
]
},
"sar al, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd2 /7",
"ExpectedArm64ASM": [
"sxtb x20, w4",
"asr w21, w20, w5",
"cbz w5, #+0x18",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv",
"bfxil x4, x21, #0, #8"
]
},
"rol ax, cl": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x24",
"mov w20, w4",
"bfi w20, w4, #16, #16",
"neg w21, w5",
"ror w20, w20, w21",
"bfxil x4, x20, #0, #16",
"rmif x20, #63, #nzCv",
"eor w20, w20, w20, lsr #15",
"rmif x20, #0, #nzcV"
]
},
"rol eax, cl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x18",
"neg w20, w5",
"ror w4, w4, w20",
"rmif x4, #63, #nzCv",
"eor w20, w4, w4, lsr #31",
"rmif x20, #0, #nzcV"
]
},
"rol rax, cl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"cbz x20, #+0x18",
"neg x20, x5",
"ror x4, x4, x20",
"rmif x4, #63, #nzCv",
"eor x20, x4, x4, lsr #63",
"rmif x20, #0, #nzcV"
]
},
"ror ax, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x20",
"mov w20, w4",
"bfi w20, w4, #16, #16",
"ror w20, w20, w5",
"bfxil x4, x20, #0, #16",
"rmif x20, #14, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #14, #nzcV"
]
},
"ror eax, cl": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"cbz x20, #+0x14",
"ror w4, w4, w5",
"rmif x4, #30, #nzCv",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"ror rax, cl": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"cbz x20, #+0x14",
"ror x4, x4, x5",
"rmif x4, #62, #nzCv",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
},
"rcl ax, cl": {
"ExpectedInstructionCount": 22,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x54",
"and w20, w5, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, hs",
"bfi x22, x21, #47, #16",
"bfi x22, x23, #63, #1",
"bfi x22, x21, #30, #16",
"bfi x22, x23, #46, #1",
"bfi x22, x21, #13, #16",
"bfi x22, x23, #29, #1",
"bfxil x22, x21, #0, #16",
"neg w21, w20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #16",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x22, x20",
"rmif x20, #63, #nzCv",
"eor x20, x20, x21, lsr #15",
"rmif x20, #0, #nzcV"
]
},
"rcl eax, cl": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x34",
"lsl w20, w4, w5",
"cset w21, hs",
"neg w22, w5",
"lsr w23, w4, w22",
"orr w20, w20, w23, lsr #1",
"lsr w22, w4, w22",
"rmif x22, #63, #nzCv",
"sub w23, w5, #0x1 (1)",
"lsl w21, w21, w23",
"orr w4, w20, w21",
"eor w20, w4, w22, lsl #31",
"rmif x20, #31, #nzcV"
]
},
"rcl rax, cl": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"cbz x20, #+0x34",
"lsl x20, x4, x5",
"cset w21, hs",
"neg x22, x5",
"lsr x23, x4, x22",
"orr x20, x20, x23, lsr #1",
"lsr x22, x4, x22",
"rmif x22, #63, #nzCv",
"sub x23, x5, #0x1 (1)",
"lsl x21, x21, x23",
"orr x4, x20, x21",
"eor x20, x4, x22, lsl #63",
"rmif x20, #63, #nzcV"
]
},
"rcr ax, cl": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x34",
"cset w20, hs",
"uxth w21, w4",
"bfi x21, x20, #16, #1",
"bfi x21, x21, #17, #17",
"bfi x21, x21, #34, #17",
"lsr w20, w21, w5",
"bfxil x4, x20, #0, #16",
"sub w22, w5, #0x1 (1)",
"lsr w21, w21, w22",
"rmif x21, #63, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #14, #nzcV"
]
},
"rcr eax, cl": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x34",
"lsr w20, w4, w5",
"cset w21, hs",
"neg w22, w5",
"lsl w23, w4, w22",
"orr w20, w20, w23, lsl #1",
"sub w23, w5, #0x1 (1)",
"lsr w23, w4, w23",
"rmif x23, #63, #nzCv",
"lsl w21, w21, w22",
"orr w4, w20, w21",
"eor w20, w4, w4, lsr #1",
"rmif x20, #30, #nzcV"
]
},
"rcr rax, cl": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"cbz x20, #+0x34",
"lsr x20, x4, x5",
"cset w21, hs",
"neg x22, x5",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
"sub x23, x5, #0x1 (1)",
"lsr x23, x4, x23",
"rmif x23, #63, #nzCv",
"lsl x21, x21, x22",
"orr x4, x20, x21",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV"
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"cbz w5, #+0x24",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV",
"bfxil x4, x20, #0, #16"
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"cbz w5, #+0x1c",
"ands w26, w20, w20",
"neg w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV",
"mov x4, x20"
]
},
"shl rax, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl x20, x4, x5",
"cbz x5, #+0x1c",
"ands x26, x20, x20",
"neg x0, x5",
"lsr x0, x4, x0",
"eor x2, x4, x20",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV",
"mov x4, x20"
]
},
"shr ax, cl": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, w5",
"cbz w5, #+0x20",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w21",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV",
"bfxil x4, x21, #0, #16"
]
},
"shr eax, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"lsr w20, w4, w5",
"cbz w5, #+0x1c",
"ands w26, w20, w20",
"sub x0, x5, #0x1 (1)",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #31, #nzcV",
"mov x4, x20"
]
},
"shr rax, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"lsr x20, x4, x5",
"cbz x5, #+0x1c",
"ands x26, x20, x20",
"sub x0, x5, #0x1 (1)",
"lsr x0, x4, x0",
"eor x2, x4, x20",
"rmif x0, #63, #nzCv",
"rmif x2, #63, #nzcV",
"mov x4, x20"
]
},
"sar ax, cl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"sxth x20, w4",
"asr w21, w20, w5",
"cbz w5, #+0x18",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv",
"bfxil x4, x21, #0, #16"
]
},
"sar eax, cl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"asr w20, w4, w5",
"cbz w5, #+0x14",
"ands w26, w20, w20",
"sub x0, x5, #0x1 (1)",
"lsr w0, w4, w0",
"rmif x0, #63, #nzCv",
"mov x4, x20"
]
},
"sar rax, cl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"asr x20, x4, x5",
"cbz x5, #+0x14",
"ands x26, x20, x20",
"sub x0, x5, #0x1 (1)",
"lsr x0, x4, x0",
"rmif x0, #63, #nzCv",
"mov x4, x20"
]
},
"test bl, 1": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf6 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"not bl": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"eor x7, x7, #0xff"
]
},
"neg bl": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"cfinv",
"bfxil x7, x26, #0, #8"
]
},
"mul bl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf6 /4",
"ExpectedArm64ASM": [
"uxtb x20, w7",
"uxtb x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"ubfx x20, x20, #8, #8",
"cmp x20, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul bl": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf6 /5",
"ExpectedArm64ASM": [
"sxtb x20, w7",
"sxtb x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"sbfx x21, x20, #8, #8",
"sbfx x20, x20, #7, #1",
"cmp x21, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"div bl": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xf6 /6",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxth w21, w4",
"uxth w0, w21",
"uxth w1, w20",
"udiv w22, w0, w1",
"uxth w0, w21",
"uxth w1, w20",
"udiv w2, w0, w1",
"msub w20, w2, w1, w0",
"bfi x22, x20, #8, #8",
"bfxil x4, x22, #0, #16"
]
},
"idiv bl": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /7",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxth w21, w4",
"sxth x21, w21",
"sxtb x20, w20",
"sdiv x22, x21, x20",
"sdiv x0, x21, x20",
"msub x20, x0, x20, x21",
"bfi x22, x20, #8, #8",
"bfxil x4, x22, #0, #16"
]
},
"test bx, 1": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"test ebx, 1": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w7, #0x1"
]
},
"test rbx, 1": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x7, #0x1"
]
},
"test bx, -1": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x26, x7",
"cmn wzr, w26, lsl #16"
]
},
"test ebx, -1": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w7, w7"
]
},
"test rbx, -1": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x7, x7"
]
},
"neg bx": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"cfinv",
"bfxil x7, x26, #0, #16"
]
},
"neg ebx": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs w26, w7",
"cfinv",
"mov x7, x26"
]
},
"neg rbx": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs x26, x7",
"cfinv",
"mov x7, x26"
]
},
"mul bx": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"uxth x20, w7",
"uxth x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"ubfx x20, x20, #16, #16",
"bfxil x6, x20, #0, #16",
"cmp x20, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq"
]
},
"mul ebx": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"mul x20, x20, x21",
"mov w4, w20",
"lsr x6, x20, #32",
"cmp x6, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq"
]
},
"mul rbx": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"mov x4, x20",
"cmp x6, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul bx": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"sxth x20, w7",
"sxth x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"sbfx x21, x20, #16, #16",
"bfxil x6, x21, #0, #16",
"sbfx x20, x20, #15, #1",
"cmp x21, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul ebx": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"sxtw x20, w7",
"sxtw x21, w4",
"mul x20, x20, x21",
"mov w4, w20",
"lsr x6, x20, #32",
"asr x21, x20, #32",
"sxtw x20, w20",
"sbfx x20, x20, #31, #1",
"cmp x21, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rbx": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"smulh x6, x7, x4",
"mul x4, x7, x4",
"asr x20, x4, #63",
"cmp x6, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"div bx": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xf7 /6",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxth w22, w6",
"uxth w0, w21",
"bfi w0, w22, #16, #16",
"udiv w23, w0, w20",
"uxth w0, w21",
"bfi w0, w22, #16, #16",
"udiv w1, w0, w20",
"msub w20, w1, w20, w0",
"bfxil x4, x23, #0, #16",
"bfxil x6, x20, #0, #16"
]
},
"inc al": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP3 0xfe /0",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"add w26, w27, #0x1 (1)",
"setf8 w26",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"dec al": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"sub w26, w27, #0x1 (1)",
"setf8 w26",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"inc ax": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"uxth w27, w4",
"add w26, w27, #0x1 (1)",
"setf16 w26",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"inc eax": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x4, x26"
]
},
"inc rax": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x4, x26"
]
},
"dec ax": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"uxth w27, w4",
"sub w26, w27, #0x1 (1)",
"setf16 w26",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"dec eax": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x4, x26"
]
},
"dec rax": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x4, x26"
]
}
}
}
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