mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-28 06:00:48 +01:00
Billy Laws
d41cb3b69d
If a multiblock contains a call instruction, we know at the point of compilation that the instruction after that call will likely be jumped to at some point. Avoid redundant recompilation by tracking such cases and including an entrypoint for that instruction in the multiblock aswell.
349 lines
13 KiB
C++
349 lines
13 KiB
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include "Interface/IR/IR.h"
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#include "Interface/IR/IntrusiveIRList.h"
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/fextl/vector.h>
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#include <algorithm>
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#include <stdint.h>
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#include <string.h>
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namespace FEXCore::IR {
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class Pass;
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class PassManager;
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class IREmitter {
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friend class FEXCore::IR::Pass;
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friend class FEXCore::IR::PassManager;
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public:
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IREmitter(FEXCore::Utils::IntrusivePooledAllocator& ThreadAllocator)
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: DualListData {ThreadAllocator, 8 * 1024 * 1024} {
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ReownOrClaimBuffer();
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ResetWorkingList();
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}
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virtual ~IREmitter() = default;
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void ReownOrClaimBuffer() {
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DualListData.ReownOrClaimBuffer();
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}
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void DelayedDisownBuffer() {
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DualListData.DelayedDisownBuffer();
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}
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IRListView ViewIR() {
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return IRListView(&DualListData);
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}
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void ResetWorkingList();
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/**
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* @name IR allocation routines
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*
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* @{ */
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FEXCore::IR::RegisterClassType WalkFindRegClass(Ref Node);
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// These handlers add cost to the constructor and destructor
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// If it becomes an issue then blow them away
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// GCC also generates some pretty atrocious code around these
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// Use Clang!
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#define IROP_ALLOCATE_HELPERS
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#define IROP_DISPATCH_HELPERS
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#include <FEXCore/IR/IRDefines.inc>
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IRPair<IROp_Constant> _Constant(IR::OpSize Size, uint64_t Constant) {
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auto Op = AllocateOp<IROp_Constant, IROps::OP_CONSTANT>();
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LOGMAN_THROW_A_FMT(Size >= IR::OpSize::i8Bit && Size <= IR::OpSize::i64Bit, "Invalid size");
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uint64_t Mask = ~0ULL >> (64 - IR::OpSizeAsBits(Size));
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Op.first->Constant = (Constant & Mask);
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Op.first->Header.Size = Size;
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Op.first->Header.ElementSize = Size;
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return Op;
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}
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IRPair<IROp_Jump> _Jump() {
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return _Jump(InvalidNode);
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}
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IRPair<IROp_CondJump> _CondJump(Ref ssa0, CondClassType cond = {COND_NEQ}) {
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return _CondJump(ssa0, _Constant(0), InvalidNode, InvalidNode, cond, GetOpSize(ssa0));
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}
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IRPair<IROp_CondJump> _CondJump(Ref ssa0, Ref ssa1, Ref ssa2, CondClassType cond = {COND_NEQ}) {
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return _CondJump(ssa0, _Constant(0), ssa1, ssa2, cond, GetOpSize(ssa0));
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}
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// TODO: Work to remove this implicit sized Select implementation.
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IRPair<IROp_Select> _Select(uint8_t Cond, Ref ssa0, Ref ssa1, Ref ssa2, Ref ssa3, IR::OpSize CompareSize = OpSize::iUnsized) {
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if (CompareSize == OpSize::iUnsized) {
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CompareSize = std::max(OpSize::i32Bit, std::max(GetOpSize(ssa0), GetOpSize(ssa1)));
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}
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return _Select(std::max(OpSize::i32Bit, std::max(GetOpSize(ssa2), GetOpSize(ssa3))), CompareSize, CondClassType {Cond}, ssa0, ssa1, ssa2, ssa3);
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}
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IRPair<IROp_LoadMem> _LoadMem(FEXCore::IR::RegisterClassType Class, IR::OpSize Size, Ref ssa0, IR::OpSize Align = OpSize::i8Bit) {
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return _LoadMem(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);
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}
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IRPair<IROp_LoadMemTSO> _LoadMemTSO(FEXCore::IR::RegisterClassType Class, IR::OpSize Size, Ref ssa0, IR::OpSize Align = OpSize::i8Bit) {
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return _LoadMemTSO(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);
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}
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IRPair<IROp_StoreMem> _StoreMem(FEXCore::IR::RegisterClassType Class, IR::OpSize Size, Ref Addr, Ref Value, IR::OpSize Align = OpSize::i8Bit) {
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return _StoreMem(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1);
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}
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IRPair<IROp_StoreMemTSO>
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_StoreMemTSO(FEXCore::IR::RegisterClassType Class, IR::OpSize Size, Ref Addr, Ref Value, IR::OpSize Align = OpSize::i8Bit) {
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return _StoreMemTSO(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1);
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}
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Ref Invalid() {
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return InvalidNode;
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}
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void SetJumpTarget(IR::IROp_Jump* Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting Jump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op->Header.Args[0].NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetTrueJumpTarget(IR::IROp_CondJump* Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op->TrueBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetFalseJumpTarget(IR::IROp_CondJump* Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op->FalseBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetJumpTarget(IRPair<IROp_Jump> Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting Jump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op.first->Header.Args[0].NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetTrueJumpTarget(IRPair<IROp_CondJump> Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op.first->TrueBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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void SetFalseJumpTarget(IRPair<IROp_CondJump> Op, Ref Target) {
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LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Tried setting CondJump target to %{} {}",
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Target->Wrapped(DualListData.ListBegin()).ID(), IR::GetName(Target->Op(DualListData.DataBegin())->Op));
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Op.first->FalseBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
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}
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/** @} */
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FEXCore::IR::RegisterClassType WalkFindRegClass(OrderedNodeWrapper ssa) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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return WalkFindRegClass(RealNode);
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}
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bool IsValueConstant(OrderedNodeWrapper ssa, uint64_t* Constant = nullptr) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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FEXCore::IR::IROp_Header* IROp = RealNode->Op(DualListData.DataBegin());
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if (IROp->Op == OP_CONSTANT) {
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auto Op = IROp->C<IR::IROp_Constant>();
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if (Constant) {
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*Constant = Op->Constant;
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}
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return true;
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}
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return false;
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}
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bool IsValueInlineConstant(OrderedNodeWrapper ssa) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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FEXCore::IR::IROp_Header* IROp = RealNode->Op(DualListData.DataBegin());
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if (IROp->Op == OP_INLINECONSTANT) {
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return true;
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}
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return false;
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}
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FEXCore::IR::IROp_Header* GetOpHeader(OrderedNodeWrapper ssa) {
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Ref RealNode = ssa.GetNode(DualListData.ListBegin());
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return RealNode->Op(DualListData.DataBegin());
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}
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Ref UnwrapNode(OrderedNodeWrapper ssa) {
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return ssa.GetNode(DualListData.ListBegin());
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}
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OrderedNodeWrapper WrapNode(Ref node) {
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return node->Wrapped(DualListData.ListBegin());
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}
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NodeIterator GetIterator(OrderedNodeWrapper wrapper) {
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return NodeIterator(DualListData.ListBegin(), DualListData.DataBegin(), wrapper);
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}
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void ReplaceAllUsesWithRange(Ref Node, Ref NewNode, AllNodesIterator Begin, AllNodesIterator End);
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void ReplaceUsesWithAfter(Ref Node, Ref NewNode, AllNodesIterator After) {
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++After;
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ReplaceAllUsesWithRange(Node, NewNode, After, AllNodesIterator(DualListData.ListBegin(), DualListData.DataBegin()));
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}
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void ReplaceUsesWithAfter(Ref Node, Ref NewNode, Ref After) {
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auto Wrapped = After->Wrapped(DualListData.ListBegin());
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AllNodesIterator It = AllNodesIterator(DualListData.ListBegin(), DualListData.DataBegin(), Wrapped);
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ReplaceUsesWithAfter(Node, NewNode, It);
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}
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void ReplaceNodeArgument(Ref Node, uint8_t Arg, Ref NewArg);
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void Remove(Ref Node);
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void RemovePostRA(Ref Node);
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void SetPackedRFLAG(bool Lower8, Ref Src);
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Ref GetPackedRFLAG(bool Lower8);
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void CopyData(const IREmitter& rhs) {
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LOGMAN_THROW_A_FMT(rhs.DualListData.DataBackingSize() <= DualListData.DataBackingSize(), "Trying to take ownership of data that is too "
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"large");
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LOGMAN_THROW_A_FMT(rhs.DualListData.ListBackingSize() <= DualListData.ListBackingSize(), "Trying to take ownership of data that is too "
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"large");
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DualListData.CopyData(rhs.DualListData);
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InvalidNode = rhs.InvalidNode->Wrapped(rhs.DualListData.ListBegin()).GetNode(DualListData.ListBegin());
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CurrentWriteCursor = rhs.CurrentWriteCursor;
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CodeBlocks = rhs.CodeBlocks;
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for (auto& CodeBlock : CodeBlocks) {
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CodeBlock = CodeBlock->Wrapped(rhs.DualListData.ListBegin()).GetNode(DualListData.ListBegin());
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}
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}
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void SetWriteCursor(Ref Node) {
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CurrentWriteCursor = Node;
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}
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// Set cursor to write before Node
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void SetWriteCursorBefore(Ref Node) {
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auto IR = ViewIR();
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auto Before = IR.at(Node);
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--Before;
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SetWriteCursor(std::get<0>(*Before));
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}
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Ref GetWriteCursor() {
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return CurrentWriteCursor;
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}
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Ref GetCurrentBlock() {
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return CurrentCodeBlock;
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}
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/**
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* @brief This creates an orphaned code node
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* The IROp backing is in the correct list but the OrderedNode lives outside of the list
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*
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* XXX: This is because we don't want code blocks to interleave with current instruction IR ops currently
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* We can change this behaviour once we remove the old BeginBlock/EndBlock types
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*
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* @return OrderedNode
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*/
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IRPair<IROp_CodeBlock> CreateCodeNode(bool EntryPoint = false, uint32_t GuestEntryOffset = 0) {
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SetWriteCursor(nullptr); // Orphan from any previous nodes
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auto ID = ViewIR().GetHeader()->BlockCount++;
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auto CodeNode = _CodeBlock(InvalidNode, InvalidNode, ID, EntryPoint, GuestEntryOffset);
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CodeBlocks.emplace_back(CodeNode);
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SetWriteCursor(nullptr); // Orphan from any future nodes
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auto Begin = _BeginBlock(CodeNode);
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CodeNode.first->Begin = Begin.Node->Wrapped(DualListData.ListBegin());
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auto EndBlock = _EndBlock(CodeNode);
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CodeNode.first->Last = EndBlock.Node->Wrapped(DualListData.ListBegin());
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return CodeNode;
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}
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/**
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* @name Links codeblocks together
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* Codeblocks are singly linked so we need to walk the list forward if the linked block isn't isn't the last
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*
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* eq.
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* CodeNode->Next -> Next
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* to
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* CodeNode->Next -> New -> Next
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*
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* @{ */
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/** @} */
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void LinkCodeBlocks(Ref CodeNode, Ref Next) {
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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FEXCore::IR::IROp_CodeBlock* CurrentIROp =
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#endif
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CodeNode->Op(DualListData.DataBegin())->CW<FEXCore::IR::IROp_CodeBlock>();
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LOGMAN_THROW_A_FMT(CurrentIROp->Header.Op == IROps::OP_CODEBLOCK, "Invalid");
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CodeNode->append(DualListData.ListBegin(), Next);
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}
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IRPair<IROp_CodeBlock> CreateNewCodeBlockAtEnd() {
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return CreateNewCodeBlockAfter(nullptr);
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}
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IRPair<IROp_CodeBlock> CreateNewCodeBlockAfter(Ref insertAfter);
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void SetCurrentCodeBlock(Ref Node);
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protected:
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void RemoveArgUses(Ref Node);
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Ref CreateNode(IROp_Header* Op) {
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uintptr_t ListBegin = DualListData.ListBegin();
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size_t Size = sizeof(OrderedNode);
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void* Ptr = DualListData.ListAllocate(Size);
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Ref Node = new (Ptr) OrderedNode();
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Node->Header.Value.SetOffset(DualListData.DataBegin(), reinterpret_cast<uintptr_t>(Op));
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if (CurrentWriteCursor) {
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CurrentWriteCursor->append(ListBegin, Node);
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}
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CurrentWriteCursor = Node;
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return Node;
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}
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Ref GetNode(uint32_t SSANode) {
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uintptr_t ListBegin = DualListData.ListBegin();
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Ref Node = reinterpret_cast<Ref>(ListBegin + SSANode * sizeof(OrderedNode));
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return Node;
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}
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Ref EmplaceOrphanedNode(Ref OldNode) {
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size_t Size = sizeof(OrderedNode);
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Ref Ptr = reinterpret_cast<Ref>(DualListData.ListAllocate(Size));
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memcpy(Ptr, OldNode, Size);
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return Ptr;
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}
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// MMX State can be either MMX (for 64bit) or x87 FPU (for 80bit)
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enum { MMXState_MMX, MMXState_X87 } MMXState = MMXState_MMX;
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// Overriden by dispatcher, stubbed for IR tests
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virtual void RecordX87Use() {}
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virtual void ChgStateX87_MMX() {}
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virtual void ChgStateMMX_X87() {}
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virtual void SaveNZCV(IROps Op) {}
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Ref CurrentWriteCursor = nullptr;
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// These could be combined with a little bit of work to be more efficient with memory usage. Isn't a big deal
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DualIntrusiveAllocatorThreadPool DualListData;
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Ref InvalidNode {};
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Ref CurrentCodeBlock {};
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fextl::vector<Ref> CodeBlocks;
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uint64_t Entry {};
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};
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} // namespace FEXCore::IR
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