mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-24 23:00:44 +02:00
Ryan Houdek
a272970559
Accesses are now classified more generically, which allows them to be optimized away more easily. XMM still needs a special case but maybe that can be changed in the future.
495 lines
18 KiB
C++
495 lines
18 KiB
C++
#include "Interface/IR/PassManager.h"
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#include "Interface/Core/OpcodeDispatcher.h"
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#include <FEXCore/Core/CoreState.h>
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namespace {
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struct ContextMemberClassification {
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size_t Offset;
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uint8_t Size;
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};
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enum LastAccessType {
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ACCESS_NONE, ///< Was never previously accessed
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ACCESS_WRITE, ///< Was fully overwritten
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ACCESS_READ, ///< Was fully read
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ACCESS_PARTIAL_WRITE, ///< Was partially written
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ACCESS_PARTIAL_READ, ///< Was partially read
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ACCESS_INVALID, ///< Accessing this is invalid
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};
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struct ContextMemberInfo {
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ContextMemberClassification Class;
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LastAccessType Accessed;
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FEXCore::IR::OrderedNode *Node;
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FEXCore::IR::OrderedNode *Node2;
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};
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using ContextInfo = std::vector<ContextMemberInfo>;
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constexpr static std::array<LastAccessType, 8> DefaultAccess = {
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ACCESS_NONE,
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ACCESS_NONE,
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ACCESS_INVALID, // PAD
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ACCESS_NONE,
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ACCESS_NONE,
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ACCESS_NONE,
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ACCESS_NONE,
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ACCESS_NONE,
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};
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static void ClassifyContextStruct(ContextInfo *ContextClassification) {
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, rip),
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sizeof(FEXCore::Core::CPUState::rip),
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},
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DefaultAccess[0],
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});
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for (size_t i = 0; i < 16; ++i) {
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, gregs[0]) + sizeof(FEXCore::Core::CPUState::gregs[0]) * i,
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sizeof(FEXCore::Core::CPUState::gregs[0]),
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},
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DefaultAccess[1],
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});
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}
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, gregs[16]),
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sizeof(uint64_t),
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},
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DefaultAccess[2], ///< NOP padding
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});
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for (size_t i = 0; i < 16; ++i) {
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, xmm[0][0]) + sizeof(FEXCore::Core::CPUState::xmm[0]) * i,
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sizeof(FEXCore::Core::CPUState::xmm[0]),
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},
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DefaultAccess[3],
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});
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}
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, gs),
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sizeof(FEXCore::Core::CPUState::gs),
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},
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DefaultAccess[4],
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});
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, fs),
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sizeof(FEXCore::Core::CPUState::fs),
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},
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DefaultAccess[5],
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});
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for (size_t i = 0; i < (sizeof(FEXCore::Core::CPUState::flags) / sizeof(FEXCore::Core::CPUState::flags[0])); ++i) {
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, flags[0]) + sizeof(FEXCore::Core::CPUState::flags[0]) * i,
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sizeof(FEXCore::Core::CPUState::flags[0]),
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},
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DefaultAccess[6],
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});
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}
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for (size_t i = 0; i < 8; ++i) {
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ContextClassification->emplace_back(ContextMemberInfo{
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ContextMemberClassification {
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offsetof(FEXCore::Core::CPUState, mm[0][0]) + sizeof(FEXCore::Core::CPUState::mm[0]) * i,
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sizeof(FEXCore::Core::CPUState::mm[0]),
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},
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DefaultAccess[7],
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});
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}
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size_t ClassifiedStructSize{};
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for (auto &it : *ContextClassification) {
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ClassifiedStructSize += it.Class.Size;
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}
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LogMan::Throw::A(ClassifiedStructSize == sizeof(FEXCore::Core::CPUState),
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"Classified CPUStruct size doesn't match real CPUState struct size! %ld != %ld",
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ClassifiedStructSize, sizeof(FEXCore::Core::CPUState));
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}
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static void ResetClassificationAccesses(ContextInfo *ContextClassification) {
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size_t Offset = 0;
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ContextClassification->at(Offset++).Accessed = DefaultAccess[0];
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for (size_t i = 0; i < 16; ++i) {
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ContextClassification->at(Offset++).Accessed = DefaultAccess[1];
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}
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ContextClassification->at(Offset++).Accessed = DefaultAccess[2];
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for (size_t i = 0; i < 16; ++i) {
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ContextClassification->at(Offset++).Accessed = DefaultAccess[3];
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}
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ContextClassification->at(Offset++).Accessed = DefaultAccess[4];
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ContextClassification->at(Offset++).Accessed = DefaultAccess[5];
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for (size_t i = 0; i < (sizeof(FEXCore::Core::CPUState::flags) / sizeof(FEXCore::Core::CPUState::flags[0])); ++i) {
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ContextClassification->at(Offset++).Accessed = DefaultAccess[6];
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}
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for (size_t i = 0; i < 8; ++i) {
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ContextClassification->at(Offset++).Accessed = DefaultAccess[7];
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}
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}
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struct BlockInfo {
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std::vector<FEXCore::IR::OrderedNode *> Predecessors;
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std::vector<FEXCore::IR::OrderedNode *> Successors;
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ContextInfo IncomingClassifiedStruct;
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ContextInfo OutgoingClassifiedStruct;
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};
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class RCLSE final : public FEXCore::IR::Pass {
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public:
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RCLSE() {
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ClassifyContextStruct(&ClassifiedStruct);
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}
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bool Run(FEXCore::IR::OpDispatchBuilder *Disp) override;
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private:
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ContextInfo ClassifiedStruct;
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std::unordered_map<FEXCore::IR::OrderedNodeWrapper::NodeOffsetType, BlockInfo> OffsetToBlockMap;
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ContextMemberInfo *FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size);
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ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2 = nullptr);
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ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2 = nullptr);
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void CalculateControlFlowInfo(FEXCore::IR::OpDispatchBuilder *Disp);
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// Block local Passes
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bool RedundantStoreLoadElimination(FEXCore::IR::OpDispatchBuilder *Disp);
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};
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ContextMemberInfo *RCLSE::FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size) {
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ContextMemberInfo *Info{};
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// Just linearly scan to find the info
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for (size_t i = 0; i < ClassifiedInfo->size(); ++i) {
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ContextMemberInfo &LocalInfo = ClassifiedInfo->at(i);
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if (LocalInfo.Class.Offset >= Offset &&
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(LocalInfo.Class.Offset + LocalInfo.Class.Size) > Offset) {
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Info = &LocalInfo;
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break;
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}
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}
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LogMan::Throw::A(Info != nullptr, "Couldn't find Context Member to record to");
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return Info;
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}
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ContextMemberInfo *RCLSE::RecordAccess(ContextMemberInfo *Info, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2) {
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LogMan::Throw::A((Offset + Size) <= (Info->Class.Offset + Info->Class.Size), "Access to context item went over member size");
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LogMan::Throw::A(Info->Accessed != ACCESS_INVALID, "Tried to access invalid member");
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// If we aren't fully overwriting the member then it is a partial write that we need to track
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if (Size < Info->Class.Size) {
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AccessType = AccessType == ACCESS_WRITE ? ACCESS_PARTIAL_WRITE : ACCESS_PARTIAL_READ;
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}
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if (Size > Info->Class.Size) {
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LogMan::Msg::A("Can't handle this");
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}
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Info->Accessed = AccessType;
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Info->Node = Node;
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Info->Node2 = Node2;
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return Info;
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}
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ContextMemberInfo *RCLSE::RecordAccess(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *Node2) {
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ContextMemberInfo *Info = FindMemberInfo(ClassifiedInfo, Offset, Size);
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return RecordAccess(Info, Offset, Size, AccessType, Node, Node2);
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}
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void RCLSE::CalculateControlFlowInfo(FEXCore::IR::OpDispatchBuilder *Disp) {
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using namespace FEXCore;
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using namespace FEXCore::IR;
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OffsetToBlockMap.clear();
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auto CurrentIR = Disp->ViewIR();
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uintptr_t ListBegin = CurrentIR.GetListData();
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uintptr_t DataBegin = CurrentIR.GetData();
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auto Begin = CurrentIR.begin();
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auto Op = Begin();
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OrderedNode *RealNode = Op->GetNode(ListBegin);
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auto HeaderOp = RealNode->Op(DataBegin)->CW<FEXCore::IR::IROp_IRHeader>();
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LogMan::Throw::A(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader");
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// Walk the list and calculate the control flow
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OrderedNode *BlockNode = HeaderOp->Blocks.GetNode(ListBegin);
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while (1) {
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auto BlockIROp = BlockNode->Op(DataBegin)->CW<FEXCore::IR::IROp_CodeBlock>();
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LogMan::Throw::A(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
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BlockInfo *CurrentBlock = &OffsetToBlockMap.try_emplace(BlockNode->Wrapped(ListBegin).ID()).first->second;
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// We grab these nodes this way so we can iterate easily
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auto CodeBegin = CurrentIR.at(BlockIROp->Begin);
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auto CodeLast = CurrentIR.at(BlockIROp->Last);
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while (1) {
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auto CodeOp = CodeBegin();
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OrderedNode *CodeNode = CodeOp->GetNode(ListBegin);
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auto IROp = CodeNode->Op(DataBegin);
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switch (IROp->Op) {
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case IR::OP_CONDJUMP: {
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auto Op = IROp->CW<IR::IROp_CondJump>();
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OrderedNode *TrueTargetNode = Op->Header.Args[1].GetNode(ListBegin);
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OrderedNode *FalseTargetNode = Op->Header.Args[2].GetNode(ListBegin);
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CurrentBlock->Successors.emplace_back(TrueTargetNode);
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CurrentBlock->Successors.emplace_back(FalseTargetNode);
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{
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auto Block = &OffsetToBlockMap.try_emplace(Op->Header.Args[1].ID()).first->second;
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Block->Predecessors.emplace_back(BlockNode);
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}
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{
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auto Block = &OffsetToBlockMap.try_emplace(Op->Header.Args[2].ID()).first->second;
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Block->Predecessors.emplace_back(BlockNode);
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}
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break;
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}
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case IR::OP_JUMP: {
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auto Op = IROp->CW<IR::IROp_Jump>();
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OrderedNode *TargetNode = Op->Header.Args[0].GetNode(ListBegin);
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CurrentBlock->Successors.emplace_back(TargetNode);
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{
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auto Block = OffsetToBlockMap.try_emplace(Op->Header.Args[0].ID()).first;
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Block->second.Predecessors.emplace_back(BlockNode);
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}
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break;
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}
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default: break;
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}
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// CodeLast is inclusive. So we still need to dump the CodeLast op as well
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if (CodeBegin == CodeLast) {
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break;
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}
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++CodeBegin;
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}
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if (BlockIROp->Next.ID() == 0) {
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break;
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} else {
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BlockNode = BlockIROp->Next.GetNode(ListBegin);
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}
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}
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}
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/**
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* @brief This pass removes redundant pairs of storecontext and loadcontext ops
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*
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* eg.
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* %ssa26 i128 = LoadMem %ssa25 i64, 0x10
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* (%%ssa27) StoreContext %ssa26 i128, 0x10, 0xb0
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* %ssa28 i128 = LoadContext 0x10, 0x90
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* %ssa29 i128 = LoadContext 0x10, 0xb0
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* Converts to
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* %ssa26 i128 = LoadMem %ssa25 i64, 0x10
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* (%%ssa27) StoreContext %ssa26 i128, 0x10, 0xb0
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* %ssa28 i128 = LoadContext 0x10, 0x90
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* %ssa29 i128 = VBitcast %ssa26 i128
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*
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* eg.
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* %ssa6 i128 = LoadContext 0x10, 0x90
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* %ssa7 i128 = LoadContext 0x10, 0x90
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* %ssa8 i128 = VXor %ssa7 i128, %ssa6 i128
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* Converts to
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* %ssa6 i128 = LoadContext 0x10, 0x90
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* %ssa7 i128 = VXor %ssa6 i128, %ssa6 i128
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*
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* eg.
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* (%%ssa189) StoreContext %ssa188 i128, 0x10, 0xa0
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* %ssa190 i128 = LoadContext 0x10, 0x90
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* %ssa191 i128 = VBitcast %ssa188 i128
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* %ssa192 i128 = VAdd %ssa191 i128, %ssa190 i128, 0x10, 0x4
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* (%%ssa193) StoreContext %ssa192 i128, 0x10, 0xa0
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* Converts to
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* %ssa173 i128 = LoadContext 0x10, 0x90
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* %ssa174 i128 = VBitcast %ssa172 i128
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* %ssa175 i128 = VAdd %ssa174 i128, %ssa173 i128, 0x10, 0x4
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* (%%ssa176) StoreContext %ssa175 i128, 0x10, 0xa0
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*/
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bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::OpDispatchBuilder *Disp) {
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using namespace FEXCore;
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using namespace FEXCore::IR;
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bool Changed = false;
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auto CurrentIR = Disp->ViewIR();
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uintptr_t ListBegin = CurrentIR.GetListData();
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uintptr_t DataBegin = CurrentIR.GetData();
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auto OriginalWriteCursor = Disp->GetWriteCursor();
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auto Begin = CurrentIR.begin();
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auto Op = Begin();
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OrderedNode *RealNode = Op->GetNode(ListBegin);
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auto HeaderOp = RealNode->Op(DataBegin)->CW<FEXCore::IR::IROp_IRHeader>();
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LogMan::Throw::A(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader");
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// Walk the list and calculate the control flow
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OrderedNode *BlockNode = HeaderOp->Blocks.GetNode(ListBegin);
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ContextInfo LocalInfo;
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ClassifyContextStruct(&LocalInfo);
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while (1) {
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auto BlockIROp = BlockNode->Op(DataBegin)->CW<FEXCore::IR::IROp_CodeBlock>();
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LogMan::Throw::A(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
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ResetClassificationAccesses(&LocalInfo);
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// We grab these nodes this way so we can iterate easily
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auto CodeBegin = CurrentIR.at(BlockIROp->Begin);
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auto CodeLast = CurrentIR.at(BlockIROp->Last);
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while (1) {
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auto CodeOp = CodeBegin();
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OrderedNode *CodeNode = CodeOp->GetNode(ListBegin);
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auto IROp = CodeNode->Op(DataBegin);
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if (IROp->Op == OP_STORECONTEXT) {
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auto Op = IROp->CW<IR::IROp_StoreContext>();
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RecordAccess(&LocalInfo, Op->Offset, Op->Size, ACCESS_WRITE, Op->Header.Args[0].GetNode(ListBegin), CodeNode);
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}
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else if (IROp->Op == OP_LOADCONTEXT) {
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auto Op = IROp->CW<IR::IROp_LoadContext>();
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auto Info = FindMemberInfo(&LocalInfo, Op->Offset, Op->Size);
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LastAccessType LastAccess = Info->Accessed;
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OrderedNode *LastNode = Info->Node;
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RecordAccess(Info, Op->Offset, Op->Size, ACCESS_READ, CodeNode);
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// XXX: For some reason this is bugged and I (HdkR) hasn't looked in to it
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if (LastAccess == ACCESS_WRITE &&
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Info->Accessed == ACCESS_READ && false) {
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// If the last store matches this load value then we can replace the loaded value with the previous valid one
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if (Op->Offset >= offsetof(FEXCore::Core::CPUState, xmm[0]) &&
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Op->Offset <= offsetof(FEXCore::Core::CPUState, xmm[15])) {
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Disp->SetWriteCursor(CodeNode);
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// XMM needs a bit of special help
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auto BitCast = Disp->_VBitcast(LastNode);
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Disp->ReplaceAllUsesWithInclusive(CodeNode, BitCast, CodeBegin, CodeLast);
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RecordAccess(Info, Op->Offset, Op->Size, ACCESS_READ, BitCast);
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}
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else {
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Disp->ReplaceAllUsesWithInclusive(CodeNode, LastNode, CodeBegin, CodeLast);
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RecordAccess(Info, Op->Offset, Op->Size, ACCESS_READ, LastNode);
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}
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if (CodeNode->GetUses() == 0)
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Disp->Remove(CodeNode);
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Changed = true;
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}
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else if (LastAccess == ACCESS_READ &&
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Info->Accessed == ACCESS_READ) {
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// Did we read and then read again?
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Disp->ReplaceAllUsesWithInclusive(CodeNode, LastNode, CodeBegin, CodeLast);
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RecordAccess(Info, Op->Offset, Op->Size, ACCESS_READ, LastNode);
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if (CodeNode->GetUses() == 0)
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Disp->Remove(CodeNode);
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Changed = true;
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}
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}
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else if (IROp->Op == OP_STOREFLAG) {
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auto Op = IROp->CW<IR::IROp_StoreFlag>();
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auto Info = FindMemberInfo(&LocalInfo, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1);
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LastAccessType LastAccess = Info->Accessed;
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OrderedNode *LastNode2 = Info->Node2;
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if (LastAccess == ACCESS_WRITE) {
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// If we last wrote to this flag then we can eliminate the last store
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// LastNode2 = node doing the write
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Disp->Remove(LastNode2);
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RecordAccess(&LocalInfo, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1, ACCESS_WRITE, Op->Header.Args[0].GetNode(ListBegin), CodeNode);
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Changed = true;
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}
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else {
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RecordAccess(&LocalInfo, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1, ACCESS_WRITE, Op->Header.Args[0].GetNode(ListBegin), CodeNode);
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}
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}
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else if (IROp->Op == OP_LOADFLAG) {
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auto Op = IROp->CW<IR::IROp_LoadFlag>();
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auto Info = FindMemberInfo(&LocalInfo, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1);
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LastAccessType LastAccess = Info->Accessed;
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OrderedNode *LastNode = Info->Node;
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if (LastAccess == ACCESS_WRITE) { // 1 byte so always a full write
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// If the last store matches this load value then we can replace the loaded value with the previous valid one
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Disp->SetWriteCursor(CodeNode);
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auto Res = Disp->_Bfe(1, 0, LastNode);
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Disp->ReplaceAllUsesWithInclusive(CodeNode, Res, CodeBegin, CodeLast);
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if (CodeNode->GetUses() == 0)
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Disp->Remove(CodeNode);
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RecordAccess(Info, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1, ACCESS_READ, Res);
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Changed = true;
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}
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else if (LastAccess == ACCESS_READ) {
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|
Disp->SetWriteCursor(CodeNode);
|
|
Disp->ReplaceAllUsesWithInclusive(CodeNode, LastNode, CodeBegin, CodeLast);
|
|
RecordAccess(Info, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1, ACCESS_READ, CodeNode);
|
|
|
|
if (CodeNode->GetUses() == 0)
|
|
Disp->Remove(CodeNode);
|
|
Changed = true;
|
|
}
|
|
}
|
|
else if (IROp->Op == OP_STORECONTEXTINDEXED ||
|
|
IROp->Op == OP_LOADCONTEXTINDEXED) {
|
|
// We can't track through these
|
|
ResetClassificationAccesses(&LocalInfo);
|
|
}
|
|
|
|
// CodeLast is inclusive. So we still need to dump the CodeLast op as well
|
|
if (CodeBegin == CodeLast) {
|
|
break;
|
|
}
|
|
++CodeBegin;
|
|
}
|
|
|
|
if (BlockIROp->Next.ID() == 0) {
|
|
break;
|
|
} else {
|
|
BlockNode = BlockIROp->Next.GetNode(ListBegin);
|
|
}
|
|
}
|
|
|
|
Disp->SetWriteCursor(OriginalWriteCursor);
|
|
|
|
return Changed;
|
|
}
|
|
|
|
bool RCLSE::Run(FEXCore::IR::OpDispatchBuilder *Disp) {
|
|
ResetClassificationAccesses(&ClassifiedStruct);
|
|
CalculateControlFlowInfo(Disp);
|
|
bool Changed = false;
|
|
Changed |= RedundantStoreLoadElimination(Disp);
|
|
|
|
return Changed;
|
|
}
|
|
|
|
}
|
|
|
|
namespace FEXCore::IR {
|
|
|
|
FEXCore::IR::Pass* CreateContextLoadStoreElimination() {
|
|
return new RCLSE{};
|
|
}
|
|
|
|
}
|