Alyssa Rosenzweig d7ff1b78fb IR: handle 8/16-bit AddNZCV/SubNZCV ...

we can do it more effectively than the current s/w lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-02-12 12:36:09 -04:00

..

Common

FEXCore: Moves BitUtils to FHU

2023-12-25 06:38:51 -08:00

Interface

IR: handle 8/16-bit AddNZCV/SubNZCV

2024-02-12 12:36:09 -04:00

Utils

SpinWaitLock: Removes unused variable in spin-loop fallback

2024-02-05 07:22:52 -08:00

CMakeLists.txt

FEXCore/Utils: Rename FutexSpinWait to SpinWaitLock

2024-01-17 10:19:38 -08:00