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FEX-Emu--FEX/FEXCore/Source/Interface/IR
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Alyssa Rosenzweig feb67658e1 RegisterAllocationPass: exploit new IR 
Now that we can just set registers directly, we can simplify RA a lot. All the
Map/Unmap nonsense - it all goes away. We just assign registers as we go and
everything clicks into place naturally.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2025-05-19 13:42:59 -04:00
..
Passes
RegisterAllocationPass: exploit new IR
2025-05-19 13:42:59 -04:00
AOTIR.cpp
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
AOTIR.h
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
IntrusiveIRList.h
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
IR.h
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
IR.json
IR: extend the IR header with RA info
2025-05-19 13:42:59 -04:00
IRDumper.cpp
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
IREmitter.cpp
Revert "Enable RA of SVE Predicate Registers"
2025-01-29 11:56:19 +01:00
IREmitter.h
IR/IREmitter: static analysis warnings
2025-03-27 04:26:40 -07:00
Passes.h
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00
PassManager.cpp
IR: drop RA validation
2025-05-16 15:18:06 -04:00
PassManager.h
Various: More static analysis warnings cleanup
2025-03-12 17:27:41 -07:00
RegisterAllocationData.h
IR: drop RegisterAllocationData
2025-05-19 13:42:59 -04:00