Alyssa Rosenzweig e5cb583cc0 OpcodeDispatcher: optimize 8-bit rol ...

rotate right by less than 8:

  ror(________________7654321076543120, ...)

rotate left by less than 8:

  rol(76543210________________76543210, ...)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-08-19 10:40:53 -04:00

..

Common

F80: Drop dependency on state stored in TLS

2024-07-31 18:51:42 +01:00

Interface

OpcodeDispatcher: optimize 8-bit rol

2024-08-19 10:40:53 -04:00

Utils

PR review comments

2024-08-16 10:21:18 -07:00

CMakeLists.txt

FEXCore: Disable vixl linking if vixl disasm or simulator is disabled

2024-08-16 07:29:41 -07:00