Ryan Houdek 80ae3e632d Arm64: Optimize {Load,Store}ContextIndexed address generation ...

All of these IR operations were being fairly inefficient in their
address calculation. All of these are known using power of 2 stride
indexing. So all of these can be converted from three instructions to
one.

These are always used for x87 stack accesses so each one gets an
improvement.

Before:
```asm
0x0000ffff6a800248  d2800200    mov x0, #0x10
0x0000ffff6a80024c  9b007e80    mul x0, x20, x0
0x0000ffff6a800250  8b000380    add x0, x28, x0
0x0000ffff6a800254  fd417805    ldr d5, [x0, #752]
```

After:
```asm
0x0000ffff91e80240  8b141380    add x0, x28, x20, lsl #4
0x0000ffff91e80244  fd417805    ldr d5, [x0, #752]
```

2023-07-17 22:59:33 -07:00

..

ccpp.yml

Arm64: Optimize {Load,Store}ContextIndexed address generation

2023-07-17 22:59:33 -07:00

glibc_fault.yml

Arm64: Optimize {Load,Store}ContextIndexed address generation

2023-07-17 22:59:33 -07:00

vixl_simulator.yml

github: Updates some actions to v3

2023-05-22 10:39:13 -07:00