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Ryan Houdek
7e66508016
x86's REP STOS instruction is a memset (with element size!) with the ability to choose a direction of execution. Additionally it has a feature where if it faults part-way through the copy, an application can catch the fault and continue afterwards to know how many bytes got copied. RCX is the counter which decrements for each element, and RDI is the memory pointer. On fault these will reflect the last location that was attempted to be written. FEX doesn't support this behaviour which makes our lives easier. Without supporting that feature, this turns in to a directional memset by element size. Let's remove all the multiple blocks and just emit a single IR operation to improve performance of the JIT. Our generated code here was terrible, the IR was terrible, multiblock is always slow with RA. Just a general overall improvement. With profiling pressure-vessel this change deletes the hottest block that appeared in the trace. This instruction is very commonly used for memsetting a region to zero so it should be quite fast. We can also optimize REP MOVS in the future with a Memcpy IR operation in a similar fashion. Additionally in the future these can be optimized to use ARM's new MOPS instructions since the most common case is memset by byte. Which is when we should expose the "Fast REP STOS" CPUID bit. Both setp/setm/sete and cpyfp/cpyfm/cpyfe match `REP STOS` and `REP MOVS` respectively.
FEXCore - Fast x86 Core emulation library
This is the core emulation library that is used for the FEX emulator project. This project aims to provide a fast and functional x86-64 emulation library that can meet and surpass other x86-64 emulation libraries.
Goals
- Be as fast as possible, beating and exceeding current options for x86-64 emulation
- 25% - 50% lower performance than native code would be desired target
- Use an IR to efficiently translate x86-64 to our host architecture
- Support a tiered recompiler to allow for fast runtime performance
- Support offline compilation and offline tooling for inspection and performance analysis
- Support threaded emulation. Including emulating x86-64's strong memory model on weak memory model architectures
- Support a significant portion of the x86-64 instruction space.
- Including MMX, SSE, SSE2, SSE3, SSSE3, and SSE4*
- Support fallback routines for uncommonly used x86-64 instructions
- Including x87 and 3DNow!
- Only support userspace emulation.
- All x86-64 instructions run as if they are under CPL-3(userland) security layer
- Minimal Linux Syscall emulation for testing purposes
- Portable library implementation in order to support easy integration in to applications
Target Host Architecture
The target host architecture for this library is AArch64. Specifically the ARMv8.1 version or newer. The CPU IR is designed with AArch64 in mind but should allow for other architectures as well. x86-64 host support is available for ease of development, but is not a priority.
Not desired
- Kernel space emulation
- CPL0-2 emulation
- Real Mode, Protected Mode, Virtual-8086 Mode, System Management Mode
- IRQs
- SVM
- "Cycle Accurate" emulation