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Merge pull request #4538 from Sonicadvance1/fex_interpreters_are_dancing

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JIT: Move interpreter ABI handlers in to the dispatcher
This commit is contained in:
Ryan Houdek authored and GitHub committed 2025-04-30 11:51:29 -07:00
2 parents e1d032b5a6 75a39c8939
commit 00ff549044
39 files changed
+37176 -171834
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FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+10 -6
View File
@@ -719,8 +719,8 @@ void Arm64Emitter::SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs, uint3
const auto Reg = StaticFPRegisters[i];
if (((1U << Reg.Idx()) & FPRSpillMask) != 0) {
mov(ARMEmitter::Size::i64Bit, TMP4.R(), offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
st1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B, STATE.R(), TMP4.R());
mov(ARMEmitter::Size::i64Bit, TmpReg, offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
st1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B, STATE.R(), TmpReg);
}
}
} else {
@@ -801,8 +801,8 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
const auto Reg = StaticFPRegisters[i];
if (((1U << Reg.Idx()) & FPRFillMask) != 0) {
mov(ARMEmitter::Size::i64Bit, TMP4.R(), offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
ld1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B.Zeroing(), STATE.R(), TMP4.R());
mov(ARMEmitter::Size::i64Bit, TmpReg, offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
ld1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B.Zeroing(), STATE.R(), TmpReg);
}
}
} else {
@@ -960,7 +960,7 @@ void Arm64Emitter::PopGeneralRegisters(std::span<const ARMEmitter::Register> Reg
}
}
void Arm64Emitter::PushDynamicRegs(ARMEmitter::Register TmpReg) {
size_t Arm64Emitter::PushDynamicRegs(ARMEmitter::Register TmpReg) {
const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
const auto GPRSize = GeneralRegistersNotPreserved.size() * Core::CPUState::GPR_REG_SIZE;
const auto FPRRegSize = CanUseSVE256 ? 32 : 16;
@@ -979,6 +979,8 @@ void Arm64Emitter::PushDynamicRegs(ARMEmitter::Register TmpReg) {
// Push the general registers.
PushGeneralRegisters(TmpReg, GeneralRegistersNotPreserved);
return SPOffset;
}
void Arm64Emitter::PopDynamicRegs() {
@@ -991,7 +993,7 @@ void Arm64Emitter::PopDynamicRegs() {
PopGeneralRegisters(GeneralRegistersNotPreserved);
}
void Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs) {
size_t Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs) {
const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
const auto FPRRegSize = CanUseSVE256 ? 32 : 16;
@@ -1038,6 +1040,8 @@ void Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool
// Push the general registers.
PushGeneralRegisters(TmpReg, DynamicGPRs);
return SPOffset;
}
void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
+6 -8
View File
@@ -119,9 +119,6 @@ protected:
// Returning REG_INVALID if there was no mapping.
FEXCore::X86State::X86Reg GetX86RegRelationToARMReg(ARMEmitter::Register Reg);
// NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled
// and FPRs are being spilled or filled. If only GPRs are spilled/filled, then
// TMP4 is left alone.
void SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U,
std::optional<ARMEmitter::Register> OptionalReg = std::nullopt,
@@ -141,7 +138,8 @@ protected:
void PopVectorRegisters(bool SVERegs, std::span<const ARMEmitter::VRegister> VRegs);
void PopGeneralRegisters(std::span<const ARMEmitter::Register> Regs);
void PushDynamicRegs(ARMEmitter::Register TmpReg);
// Returns stack size consumed for pushing dynamic registers.
size_t PushDynamicRegs(ARMEmitter::Register TmpReg);
void PopDynamicRegs();
void PushCalleeSavedRegisters();
@@ -157,15 +155,15 @@ protected:
// Callee Saved:
// - X9-X15, X19-X29, X31
// - Low 128-bits of v8-v31
void SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs = true);
size_t SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs = true);
void FillForPreserveAllABICall(bool FPRs = true);
void SpillForABICall(bool SupportsPreserveAllABI, ARMEmitter::Register TmpReg, bool FPRs = true) {
size_t SpillForABICall(bool SupportsPreserveAllABI, ARMEmitter::Register TmpReg, bool FPRs = true) {
if (SupportsPreserveAllABI) {
SpillForPreserveAllABICall(TmpReg, FPRs);
return SpillForPreserveAllABICall(TmpReg, FPRs);
} else {
SpillStaticRegs(TmpReg, FPRs);
PushDynamicRegs(TmpReg);
return PushDynamicRegs(TmpReg);
}
}
FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
+429 -1
View File
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: MIT
#include "Common/SoftFloat.h"
#include "Interface/Context/Context.h"
#include "Interface/Core/Dispatcher/Dispatcher.h"
#include "Interface/Core/LookupCache.h"
@@ -30,7 +31,7 @@ static void SleepThread(FEXCore::Context::ContextImpl* CTX, FEXCore::Core::CpuSt
CTX->SyscallHandler->SleepThread(CTX, Frame);
}
constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;
constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 4;
Dispatcher::Dispatcher(FEXCore::Context::ContextImpl* ctx)
: Arm64Emitter(ctx, FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true), MAX_DISPATCHER_CODE_SIZE)
@@ -541,6 +542,32 @@ void Dispatcher::EmitDispatcher() {
LUREMHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
LREMHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));
// Interpreter fallbacks
{
constexpr static std::array<FallbackABI, FABI_UNKNOWN> ABIS {{
FABI_F80_I16_F32_PTR,
FABI_F80_I16_F64_PTR,
FABI_F80_I16_I16_PTR,
FABI_F80_I16_I32_PTR,
FABI_F32_I16_F80_PTR,
FABI_F64_I16_F80_PTR,
FABI_F64_I16_F64_PTR,
FABI_F64_I16_F64_F64_PTR,
FABI_I16_I16_F80_PTR,
FABI_I32_I16_F80_PTR,
FABI_I64_I16_F80_PTR,
FABI_I64_I16_F80_F80_PTR,
FABI_F80_I16_F80_PTR,
FABI_F80_I16_F80_F80_PTR,
FABI_I32_I64_I64_V128_V128_I16,
FABI_I32_V128_V128_I16,
}};
for (auto ABI : ABIS) {
ABIPointers[ABI] = GenerateABICall(ABI);
}
}
Bind(&l_CTX);
dc64(reinterpret_cast<uintptr_t>(CTX));
Bind(&l_Sleep);
@@ -590,6 +617,404 @@ void Dispatcher::ExecuteJITCallback(FEXCore::Core::CpuStateFrame* Frame, uint64_
#endif
uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
auto Address = GetCursorAddress<uint64_t>();
constexpr static auto FallbackPointerReg = TMP4;
constexpr static auto ABI1 = ARMEmitter::XReg::x0;
constexpr static auto ABI2 = ARMEmitter::XReg::x1;
constexpr static auto ABI3 = ARMEmitter::XReg::x2;
constexpr static auto VABI1 = ARMEmitter::VReg::v0;
constexpr static auto VABI2 = ARMEmitter::VReg::v1;
auto FillF80Result = [&]() {
if (VTMP1 != VABI1) {
mov(VTMP1.Q(), VABI1.Q());
}
FillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, true);
};
auto FillF64Result = [&]() {
if (!TMP_ABIARGS) {
fmov(VTMP1.D(), VABI1.D());
}
FillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, true);
};
auto FillF32Result = [&]() {
if (!TMP_ABIARGS) {
fmov(VTMP1.S(), VABI1.S());
}
FillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, true);
};
auto FillI64Result = [&]() {
if (!TMP_ABIARGS) {
mov(TMP1, ARMEmitter::XReg::x0);
}
FillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, true);
};
auto FillI32Result = [&]() {
if (!TMP_ABIARGS) {
mov(TMP1.W(), ARMEmitter::WReg::w0);
}
FillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, true);
};
auto FillI16Result = [&]() {
if (!TMP_ABIARGS) {
mov(TMP1, ARMEmitter::XReg::x0);
}
FillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, true);
};
switch (ABI) {
case FABI_F80_I16_F32_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
if (!TMP_ABIARGS) {
fmov(VABI1.S(), VTMP1.S());
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, float, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF80Result();
} break;
case FABI_F80_I16_F64_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
if (!TMP_ABIARGS) {
fmov(VABI1.D(), VTMP1.D());
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, double, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF80Result();
} break;
case FABI_F80_I16_I16_PTR:
case FABI_F80_I16_I32_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// tmp2 (x1/x11): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
if (!TMP_ABIARGS) {
mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, TMP2);
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x2, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, uint32_t, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF80Result();
} break;
case FABI_F32_I16_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
fmov(VABI1.D(), VTMP1.D());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<float, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF32Result();
} break;
case FABI_F64_I16_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<double, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF64Result();
} break;
case FABI_F64_I16_F64_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
if (!TMP_ABIARGS) {
fmov(VABI1.D(), VTMP1.D());
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<double, uint16_t, double, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF64Result();
} break;
case FABI_F64_I16_F64_F64_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
if (!TMP_ABIARGS) {
fmov(VABI1.D(), VTMP1.D());
fmov(VABI2.D(), VTMP2.D());
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<double, uint16_t, double, double, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF64Result();
} break;
case FABI_I16_I16_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillI16Result();
} break;
case FABI_I32_I16_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillI32Result();
} break;
case FABI_I64_I16_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint64_t, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillI64Result();
} break;
case FABI_I64_I16_F80_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
mov(VABI2.Q(), VTMP2.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint64_t, uint16_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillI64Result();
} break;
case FABI_F80_I16_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
}
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF80Result();
} break;
case FABI_F80_I16_F80_F80_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
mov(VABI2.Q(), VTMP2.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint64_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillF80Result();
} break;
case FABI_I32_I64_I64_V128_V128_I16: {
// Linux Reg/Win32 Reg:
// stack: FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
// tmp1 (x0/x10): source 1
// tmp2 (x1/x11): source 2
// tmp3 (x2/x12): source 3
const size_t OriginalSPOffset = SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP4, true);
// Load the Fallback handler pointer from the stack.
ldr(FallbackPointerReg, ARMEmitter::XReg::rsp, OriginalSPOffset);
if (!TMP_ABIARGS) {
mov(ABI1, TMP1);
mov(ABI2, TMP2);
mov(ABI3, TMP3);
mov(VABI1.Q(), VTMP1.Q());
mov(VABI2.Q(), VTMP2.Q());
}
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, uint64_t, uint64_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint16_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillI32Result();
} break;
case FABI_I32_V128_V128_I16: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
// tmp1 (x0/x10): source 1
SpillForABICall(CTX->HostFeatures.SupportsPreserveAllABI, TMP3, true);
if (!TMP_ABIARGS) {
mov(VABI1.Q(), VTMP1.Q());
mov(VABI2.Q(), VTMP2.Q());
mov(ABI1, TMP1);
}
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint16_t>(FallbackPointerReg);
} else {
blr(FallbackPointerReg);
}
FillI32Result();
} break;
case FABI_UNKNOWN:
default:
#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {}", ToUnderlying(ABI));
#endif
break;
}
// Return to JIT
ret();
return Address;
}
void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread) {
// Setup dispatcher specific pointers that need to be accessed from JIT code
{
@@ -613,6 +1038,9 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)
AArch64.LDIVHandler = LDIVHandlerAddress;
AArch64.LUREMHandler = LUREMHandlerAddress;
AArch64.LREMHandler = LREMHandlerAddress;
// Fill in the fallback handlers
InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers, &ABIPointers[0]);
}
}
FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h
+4
View File
@@ -3,7 +3,9 @@
#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
#include "Interface/Core/CPUBackend.h"
#include "Interface/Core/Interpreter/InterpreterOps.h"
#include <FEXCore/Core/CoreState.h>
#include <FEXCore/fextl/memory.h>
#ifdef VIXL_SIMULATOR
@@ -60,6 +62,7 @@ public:
uint64_t IntCallbackReturnAddress {};
uint64_t PauseReturnInstruction {};
std::array<uint64_t, FallbackABI::FABI_UNKNOWN> ABIPointers {};
/** @} */
@@ -119,6 +122,7 @@ private:
uint64_t LREMHandlerAddress {};
void EmitDispatcher();
uint64_t GenerateABICall(FallbackABI ABI);
};
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
+107 -85
View File
@@ -12,72 +12,108 @@ namespace FEXCore::CPU {
template<typename R, typename... Args>
static FallbackInfo GetFallbackInfo(R (*fn)(Args...), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
return {FABI_UNKNOWN, (void*)fn, HandlerIndex, false};
return {FABI_UNKNOWN, HandlerIndex, false};
}
template<>
FallbackInfo GetFallbackInfo(double (*fn)(uint16_t, double, FEXCore::Core::CpuStateFrame*), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
return {FABI_F64_I16_F64_PTR, (void*)fn, HandlerIndex, false};
return {FABI_F64_I16_F64_PTR, HandlerIndex, false};
}
template<>
FallbackInfo
GetFallbackInfo(double (*fn)(uint16_t, double, double, FEXCore::Core::CpuStateFrame*), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
return {FABI_F64_I16_F64_F64_PTR, (void*)fn, HandlerIndex, false};
return {FABI_F64_I16_F64_F64_PTR, HandlerIndex, false};
}
void InterpreterOps::FillFallbackIndexPointers(uint64_t* Info) {
Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4);
Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8);
Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4);
Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8);
Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2);
Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4);
Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8);
Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t);
Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t);
Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t);
Info[Core::OPINDEX_F80CMP] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle);
Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2);
Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4);
void InterpreterOps::FillFallbackIndexPointers(Core::FallbackABIInfo* Info, uint64_t* ABIHandlers) {
Info[Core::OPINDEX_F80CVTTO_4] = {ABIHandlers[FABI_F80_I16_F32_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4)};
Info[Core::OPINDEX_F80CVTTO_8] = {ABIHandlers[FABI_F80_I16_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8)};
Info[Core::OPINDEX_F80CVT_4] = {ABIHandlers[FABI_F32_I16_F80_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4)};
Info[Core::OPINDEX_F80CVT_8] = {ABIHandlers[FABI_F64_I16_F80_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8)};
Info[Core::OPINDEX_F80CVTINT_2] = {ABIHandlers[FABI_I16_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2)};
Info[Core::OPINDEX_F80CVTINT_4] = {ABIHandlers[FABI_I32_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4)};
Info[Core::OPINDEX_F80CVTINT_8] = {ABIHandlers[FABI_I64_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8)};
Info[Core::OPINDEX_F80CVTINT_TRUNC2] = {ABIHandlers[FABI_I16_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t)};
Info[Core::OPINDEX_F80CVTINT_TRUNC4] = {ABIHandlers[FABI_I32_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t)};
Info[Core::OPINDEX_F80CVTINT_TRUNC8] = {ABIHandlers[FABI_I64_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t)};
Info[Core::OPINDEX_F80CMP] = {ABIHandlers[FABI_I64_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle)};
Info[Core::OPINDEX_F80CVTTOINT_2] = {ABIHandlers[FABI_F80_I16_I16_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2)};
Info[Core::OPINDEX_F80CVTTOINT_4] = {ABIHandlers[FABI_F80_I16_I32_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4)};
// Unary
Info[Core::OPINDEX_F80ROUND] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ROUND>::handle);
Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80F2XM1>::handle);
Info[Core::OPINDEX_F80TAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80TAN>::handle);
Info[Core::OPINDEX_F80SQRT] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SQRT>::handle);
Info[Core::OPINDEX_F80SIN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SIN>::handle);
Info[Core::OPINDEX_F80COS] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80COS>::handle);
Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_EXP>::handle);
Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_SIG>::handle);
Info[Core::OPINDEX_F80BCDSTORE] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDSTORE>::handle);
Info[Core::OPINDEX_F80BCDLOAD] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDLOAD>::handle);
Info[Core::OPINDEX_F80ROUND] = {ABIHandlers[FABI_F80_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ROUND>::handle)};
Info[Core::OPINDEX_F80F2XM1] = {ABIHandlers[FABI_F80_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80F2XM1>::handle)};
Info[Core::OPINDEX_F80TAN] = {ABIHandlers[FABI_F80_I16_F80_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80TAN>::handle)};
Info[Core::OPINDEX_F80SQRT] = {ABIHandlers[FABI_F80_I16_F80_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SQRT>::handle)};
Info[Core::OPINDEX_F80SIN] = {ABIHandlers[FABI_F80_I16_F80_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SIN>::handle)};
Info[Core::OPINDEX_F80COS] = {ABIHandlers[FABI_F80_I16_F80_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80COS>::handle)};
Info[Core::OPINDEX_F80XTRACT_EXP] = {ABIHandlers[FABI_F80_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_EXP>::handle)};
Info[Core::OPINDEX_F80XTRACT_SIG] = {ABIHandlers[FABI_F80_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_SIG>::handle)};
Info[Core::OPINDEX_F80BCDSTORE] = {ABIHandlers[FABI_F80_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDSTORE>::handle)};
Info[Core::OPINDEX_F80BCDLOAD] = {ABIHandlers[FABI_F80_I16_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDLOAD>::handle)};
// Binary
Info[Core::OPINDEX_F80ADD] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ADD>::handle);
Info[Core::OPINDEX_F80SUB] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SUB>::handle);
Info[Core::OPINDEX_F80MUL] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80MUL>::handle);
Info[Core::OPINDEX_F80DIV] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80DIV>::handle);
Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FYL2X>::handle);
Info[Core::OPINDEX_F80ATAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ATAN>::handle);
Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM1>::handle);
Info[Core::OPINDEX_F80FPREM] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM>::handle);
Info[Core::OPINDEX_F80SCALE] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle);
Info[Core::OPINDEX_F80ADD] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ADD>::handle)};
Info[Core::OPINDEX_F80SUB] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SUB>::handle)};
Info[Core::OPINDEX_F80MUL] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80MUL>::handle)};
Info[Core::OPINDEX_F80DIV] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80DIV>::handle)};
Info[Core::OPINDEX_F80FYL2X] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FYL2X>::handle)};
Info[Core::OPINDEX_F80ATAN] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80ATAN>::handle)};
Info[Core::OPINDEX_F80FPREM1] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM1>::handle)};
Info[Core::OPINDEX_F80FPREM] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM>::handle)};
Info[Core::OPINDEX_F80SCALE] = {ABIHandlers[FABI_F80_I16_F80_F80_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle)};
// Double Precision
Info[Core::OPINDEX_F64SIN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle);
Info[Core::OPINDEX_F64COS] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle);
Info[Core::OPINDEX_F64TAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle);
Info[Core::OPINDEX_F64ATAN] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle);
Info[Core::OPINDEX_F64F2XM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle);
Info[Core::OPINDEX_F64FYL2X] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FYL2X>::handle);
Info[Core::OPINDEX_F64FPREM] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM>::handle);
Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle);
Info[Core::OPINDEX_F64SCALE] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle);
// Double Precision Unary
Info[Core::OPINDEX_F64SIN] = {ABIHandlers[FABI_F64_I16_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle)};
Info[Core::OPINDEX_F64COS] = {ABIHandlers[FABI_F64_I16_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle)};
Info[Core::OPINDEX_F64TAN] = {ABIHandlers[FABI_F64_I16_F64_PTR], reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle)};
Info[Core::OPINDEX_F64F2XM1] = {ABIHandlers[FABI_F64_I16_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle)};
// Double Precision Binary
Info[Core::OPINDEX_F64ATAN] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle)};
Info[Core::OPINDEX_F64FPREM] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM>::handle)};
Info[Core::OPINDEX_F64FPREM1] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle)};
Info[Core::OPINDEX_F64FYL2X] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64FYL2X>::handle)};
Info[Core::OPINDEX_F64SCALE] = {ABIHandlers[FABI_F64_I16_F64_F64_PTR],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle)};
// SSE4.2 string instructions
Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle);
Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle);
Info[Core::OPINDEX_VPCMPESTRX] = {ABIHandlers[FABI_I32_I64_I64_V128_V128_I16],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle)};
Info[Core::OPINDEX_VPCMPISTRX] = {ABIHandlers[FABI_I32_V128_V128_I16],
reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle)};
}
bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::IROp_Header* IROp, FallbackInfo* Info) {
@@ -88,11 +124,11 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
switch (Op->SrcSize) {
case IR::OpSize::i32Bit: {
*Info = {FABI_F80_I16_F32_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4, SupportsPreserveAllABI};
*Info = {FABI_F80_I16_F32_PTR, Core::OPINDEX_F80CVTTO_4, SupportsPreserveAllABI};
return true;
}
case IR::OpSize::i64Bit: {
*Info = {FABI_F80_I16_F64_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8, SupportsPreserveAllABI};
*Info = {FABI_F80_I16_F64_PTR, Core::OPINDEX_F80CVTTO_8, SupportsPreserveAllABI};
return true;
}
default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -102,11 +138,11 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
case IR::OP_F80CVT: {
switch (OpSize) {
case IR::OpSize::i32Bit: {
*Info = {FABI_F32_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4, SupportsPreserveAllABI};
*Info = {FABI_F32_I16_F80_PTR, Core::OPINDEX_F80CVT_4, SupportsPreserveAllABI};
return true;
}
case IR::OpSize::i64Bit: {
*Info = {FABI_F64_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8, SupportsPreserveAllABI};
*Info = {FABI_F64_I16_F80_PTR, Core::OPINDEX_F80CVT_8, SupportsPreserveAllABI};
return true;
}
default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -119,31 +155,25 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
switch (OpSize) {
case IR::OpSize::i16Bit: {
if (Op->Truncate) {
*Info = {FABI_I16_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2,
SupportsPreserveAllABI};
*Info = {FABI_I16_I16_F80_PTR, Core::OPINDEX_F80CVTINT_TRUNC2, SupportsPreserveAllABI};
} else {
*Info = {FABI_I16_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2,
SupportsPreserveAllABI};
*Info = {FABI_I16_I16_F80_PTR, Core::OPINDEX_F80CVTINT_2, SupportsPreserveAllABI};
}
return true;
}
case IR::OpSize::i32Bit: {
if (Op->Truncate) {
*Info = {FABI_I32_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4,
SupportsPreserveAllABI};
*Info = {FABI_I32_I16_F80_PTR, Core::OPINDEX_F80CVTINT_TRUNC4, SupportsPreserveAllABI};
} else {
*Info = {FABI_I32_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4,
SupportsPreserveAllABI};
*Info = {FABI_I32_I16_F80_PTR, Core::OPINDEX_F80CVTINT_4, SupportsPreserveAllABI};
}
return true;
}
case IR::OpSize::i64Bit: {
if (Op->Truncate) {
*Info = {FABI_I64_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8,
SupportsPreserveAllABI};
*Info = {FABI_I64_I16_F80_PTR, Core::OPINDEX_F80CVTINT_TRUNC8, SupportsPreserveAllABI};
} else {
*Info = {FABI_I64_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8,
SupportsPreserveAllABI};
*Info = {FABI_I64_I16_F80_PTR, Core::OPINDEX_F80CVTINT_8, SupportsPreserveAllABI};
}
return true;
}
@@ -152,8 +182,7 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
break;
}
case IR::OP_F80CMP: {
*Info = {FABI_I64_I16_F80_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle,
(Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP), SupportsPreserveAllABI};
*Info = {FABI_I64_I16_F80_F80_PTR, (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP), SupportsPreserveAllABI};
return true;
}
@@ -162,13 +191,11 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
switch (Op->SrcSize) {
case IR::OpSize::i16Bit: {
*Info = {FABI_F80_I16_I16_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2,
SupportsPreserveAllABI};
*Info = {FABI_F80_I16_I16_PTR, Core::OPINDEX_F80CVTTOINT_2, SupportsPreserveAllABI};
return true;
}
case IR::OpSize::i32Bit: {
*Info = {FABI_F80_I16_I32_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4,
SupportsPreserveAllABI};
*Info = {FABI_F80_I16_I32_PTR, Core::OPINDEX_F80CVTTOINT_4, SupportsPreserveAllABI};
return true;
}
default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -176,16 +203,16 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
break;
}
#define COMMON_UNARY_X87_OP(OP) \
case IR::OP_F80##OP: { \
*Info = {FABI_F80_I16_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
return true; \
#define COMMON_UNARY_X87_OP(OP) \
case IR::OP_F80##OP: { \
*Info = {FABI_F80_I16_F80_PTR, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
return true; \
}
#define COMMON_BINARY_X87_OP(OP) \
case IR::OP_F80##OP: { \
*Info = {FABI_F80_I16_F80_F80_PTR, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
return true; \
#define COMMON_BINARY_X87_OP(OP) \
case IR::OP_F80##OP: { \
*Info = {FABI_F80_I16_F80_F80_PTR, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
return true; \
}
#define COMMON_F64_OP(OP) \
@@ -231,13 +258,8 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
COMMON_F64_OP(SCALE)
// SSE4.2 Fallbacks
case IR::OP_VPCMPESTRX:
*Info = {FABI_I32_I64_I64_V128_V128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX,
SupportsPreserveAllABI};
return true;
case IR::OP_VPCMPISTRX:
*Info = {FABI_I32_V128_V128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX, SupportsPreserveAllABI};
return true;
case IR::OP_VPCMPESTRX: *Info = {FABI_I32_I64_I64_V128_V128_I16, Core::OPINDEX_VPCMPESTRX, SupportsPreserveAllABI}; return true;
case IR::OP_VPCMPISTRX: *Info = {FABI_I32_V128_V128_I16, Core::OPINDEX_VPCMPISTRX, SupportsPreserveAllABI}; return true;
default: break;
}
FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h
+2 -4
View File
@@ -13,7 +13,6 @@ struct IROp_Header;
namespace FEXCore::CPU {
enum FallbackABI {
FABI_UNKNOWN,
FABI_F80_I16_F32_PTR,
FABI_F80_I16_F64_PTR,
FABI_F80_I16_I16_PTR,
@@ -30,18 +29,17 @@ enum FallbackABI {
FABI_F80_I16_F80_F80_PTR,
FABI_I32_I64_I64_V128_V128_I16,
FABI_I32_V128_V128_I16,
FABI_UNKNOWN,
};
struct FallbackInfo {
FallbackABI ABI;
void* fn;
FEXCore::Core::FallbackHandlerIndex HandlerIndex;
bool SupportsPreserveAllABI;
};
class InterpreterOps {
public:
static void FillFallbackIndexPointers(uint64_t* Info);
static void FillFallbackIndexPointers(Core::FallbackABIInfo* Info, uint64_t* ABIHandlers);
static bool GetFallbackHandler(bool SupportsPreserveAllABI, const IR::IROp_Header* IROp, FallbackInfo* Info);
};
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/JIT.cpp
+199 -249
View File
@@ -88,392 +88,345 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::NodeID Node) {
#endif
} else {
auto FillF80Result = [&]() {
if (!TMP_ABIARGS) {
mov(VTMP1.Q(), ARMEmitter::VReg::v0.Q());
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetVReg(Node);
mov(Dst.Q(), VTMP1.Q());
};
auto FillF64Result = [&]() {
if (!TMP_ABIARGS) {
mov(VTMP1.D(), ARMEmitter::DReg::d0);
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetVReg(Node);
mov(Dst.D(), VTMP1.D());
fmov(Dst.D(), VTMP1.D());
};
auto FillF32Result = [&]() {
const auto Dst = GetVReg(Node);
fmov(Dst.S(), VTMP1.S());
};
auto FillI64Result = [&]() {
const auto Dst = GetReg(Node);
mov(Dst.X(), TMP1);
};
auto FillI32Result = [&]() {
if (!TMP_ABIARGS) {
mov(TMP1.W(), ARMEmitter::WReg::w0);
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetReg(Node);
mov(Dst.W(), TMP1.W());
};
auto FillI16Result = [&]() {
const auto Dst = GetReg(Node);
mov(Dst.W(), TMP1.W());
};
switch (Info.ABI) {
case FABI_F80_I16_F32_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
fmov(ARMEmitter::SReg::s0, Src1.S());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, float, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
fmov(VTMP1.S(), Src1.S());
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF80Result();
} break;
case FABI_F80_I16_F64_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(ARMEmitter::DReg::d0, Src1.D());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, double, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
mov(VTMP1.D(), Src1.D());
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF80Result();
} break;
case FABI_F80_I16_I16_PTR:
case FABI_F80_I16_I32_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// tmp2 (x1/x11): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetReg(IROp->Args[0].ID());
// Need to sign or zero extend this for the dispatcher handler.
if (Info.ABI == FABI_F80_I16_I16_PTR) {
sxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, Src1);
sxth(ARMEmitter::Size::i32Bit, TMP2, Src1);
} else {
mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, Src1);
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x2, STATE);
ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, uint32_t, uint64_t>(ARMEmitter::Reg::r3);
} else {
blr(ARMEmitter::Reg::r3);
mov(ARMEmitter::Size::i32Bit, TMP2, Src1);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF80Result();
} break;
case FABI_F32_I16_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.Q(), Src1.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<float, uint16_t, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
if (!TMP_ABIARGS) {
fmov(VTMP1.S(), ARMEmitter::SReg::s0);
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetVReg(Node);
fmov(Dst.S(), VTMP1.S());
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF32Result();
} break;
case FABI_F64_I16_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.Q(), Src1.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<double, uint16_t, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF64Result();
} break;
case FABI_F64_I16_F64_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.D(), Src1.D());
mov(ARMEmitter::DReg::d0, Src1.D());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<double, uint16_t, double, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF64Result();
} break;
case FABI_F64_I16_F64_F64_PTR: {
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
const auto Src2 = GetVReg(IROp->Args[1].ID());
mov(VTMP1.D(), Src1.D());
mov(VTMP2.D(), Src2.D());
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
if (!TMP_ABIARGS) {
mov(ARMEmitter::DReg::d0, VTMP1.D());
mov(ARMEmitter::DReg::d1, VTMP2.D());
}
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<double, uint16_t, double, double, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF64Result();
} break;
case FABI_I16_I16_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.Q(), Src1.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::XReg::x1, STATE);
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, uint16_t, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
if (!TMP_ABIARGS) {
mov(TMP1, ARMEmitter::XReg::x0);
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetReg(Node);
sxth(ARMEmitter::Size::i64Bit, Dst, TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillI16Result();
} break;
case FABI_I32_I16_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.Q(), Src1.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, uint16_t, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillI32Result();
} break;
case FABI_I64_I16_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): source
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.Q(), Src1.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::XReg::x1, STATE);
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint64_t, uint16_t, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
if (!TMP_ABIARGS) {
mov(TMP1, ARMEmitter::XReg::x0);
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetReg(Node);
mov(ARMEmitter::Size::i64Bit, Dst, TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillI64Result();
} break;
case FABI_I64_I16_F80_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
const auto Src2 = GetVReg(IROp->Args[1].ID());
mov(VTMP1.Q(), Src1.Q());
mov(VTMP2.Q(), Src2.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VTMP1.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
mov(ARMEmitter::VReg::v0.Q(), VTMP1.Q());
} else {
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
}
mov(ARMEmitter::XReg::x1, STATE);
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint64_t, uint16_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
if (!TMP_ABIARGS) {
mov(TMP1, ARMEmitter::XReg::x0);
}
FillForABICall(Info.SupportsPreserveAllABI, true);
const auto Dst = GetReg(Node);
mov(ARMEmitter::Size::i64Bit, Dst, TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillI64Result();
} break;
case FABI_F80_I16_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
mov(VTMP1.Q(), Src1.Q());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, FEXCore::VectorRegType, uint64_t>(ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF80Result();
} break;
case FABI_F80_I16_F80_F80_PTR: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(IROp->Args[0].ID());
const auto Src2 = GetVReg(IROp->Args[1].ID());
ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
if (!TMP_ABIARGS) {
mov(VTMP1.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
mov(ARMEmitter::VReg::v0.Q(), VTMP1.Q());
} else {
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
}
mov(VTMP1.Q(), Src1.Q());
mov(VTMP2.Q(), Src2.Q());
mov(ARMEmitter::XReg::x1, STATE);
ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<FEXCore::VectorRegType, uint16_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint64_t>(
ARMEmitter::Reg::r2);
} else {
blr(ARMEmitter::Reg::r2);
}
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP1);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillF80Result();
} break;
case FABI_I32_I64_I64_V128_V128_I16: {
// Linux Reg/Win32 Reg:
// stack: FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
// tmp1 (x0/x10): source 1
// tmp2 (x1/x11): source 2
// tmp3 (x2/x12): source 3
const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
stp<ARMEmitter::IndexType::PRE>(TMP1, ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto SrcRAX = GetReg(Op->RAX.ID());
const auto SrcRDX = GetReg(Op->RDX.ID());
const auto Control = Op->Control;
mov(TMP1, SrcRAX.X());
mov(TMP2, SrcRDX.X());
SpillForABICall(Info.SupportsPreserveAllABI, TMP3, true);
const auto Control = Op->Control;
movz(ARMEmitter::Size::i32Bit, TMP3, Control);
const auto Src1 = GetVReg(Op->LHS.ID());
const auto Src2 = GetVReg(Op->RHS.ID());
if (!TMP_ABIARGS) {
mov(ARMEmitter::XReg::x0, TMP1);
mov(ARMEmitter::XReg::x1, TMP2);
}
mov(VTMP1.Q(), Src1.Q());
mov(VTMP2.Q(), Src2.Q());
if (!TMP_ABIARGS) {
mov(VTMP1.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
mov(ARMEmitter::VReg::v0.Q(), VTMP1.Q());
} else {
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
}
movz(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, Control);
ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, uint64_t, uint64_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint16_t>(ARMEmitter::Reg::r3);
} else {
blr(ARMEmitter::Reg::r3);
}
blr(TMP4);
ldp<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::zr, ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillI32Result();
} break;
case FABI_I32_V128_V128_I16: {
SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
// Linux Reg/Win32 Reg:
// tmp4 (x4/x13): FallbackHandler
// x30: return
// vtmp1 (v0/v16): vector source 1
// vtmp2 (v1/v17): vector source 2
// tmp1 (x0/x10): source 1
const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
const auto Src1 = GetVReg(Op->LHS.ID());
const auto Src2 = GetVReg(Op->RHS.ID());
const auto Control = Op->Control;
if (!TMP_ABIARGS) {
mov(VTMP1.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
mov(ARMEmitter::VReg::v0.Q(), VTMP1.Q());
} else {
mov(ARMEmitter::VReg::v0.Q(), Src1.Q());
mov(ARMEmitter::VReg::v1.Q(), Src2.Q());
}
mov(VTMP1.Q(), Src1.Q());
mov(VTMP2.Q(), Src2.Q());
movz(ARMEmitter::Size::i32Bit, TMP1, Control);
movz(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r0, Control);
ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
GenerateIndirectRuntimeCall<uint32_t, FEXCore::VectorRegType, FEXCore::VectorRegType, uint16_t>(ARMEmitter::Reg::r1);
} else {
blr(ARMEmitter::Reg::r1);
}
ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
blr(TMP2);
ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
FillI32Result();
} break;
case FABI_UNKNOWN:
@@ -588,9 +541,6 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In
}
Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadExitFunctionLink<Arm64JITCore_ExitFunctionLink>);
// Fill in the fallback handlers
InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers);
// Platform Specific
auto& AArch64 = ThreadState->CurrentFrame->Pointers.AArch64;
FEXCore/include/FEXCore/Core/CoreState.h
+6 -1
View File
@@ -244,6 +244,11 @@ enum FallbackHandlerIndex {
OPINDEX_MAX,
};
struct FallbackABIInfo {
uint64_t ABIHandler;
uint64_t Func;
};
struct JITPointers {
struct {
@@ -262,7 +267,7 @@ struct JITPointers {
// Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3
uint64_t ExitFunctionEC {};
uint64_t FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX];
FallbackABIInfo FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX];
uint64_t NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX];
uint64_t IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_MAX];
uint64_t TelemetryValueAddresses[FEXCore::Telemetry::TYPE_LAST];
unittests/InstructionCountCI/AVX128/FMA4.json
+30 -30
View File
@@ -19,7 +19,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -33,7 +33,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -47,7 +47,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -61,7 +61,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -75,7 +75,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -89,7 +89,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -103,7 +103,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -117,7 +117,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -131,7 +131,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -145,7 +145,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -159,7 +159,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -173,7 +173,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -187,7 +187,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -201,7 +201,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -215,7 +215,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -229,7 +229,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -243,7 +243,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -257,7 +257,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -271,7 +271,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -285,7 +285,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -299,7 +299,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -313,7 +313,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -327,7 +327,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -341,7 +341,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -355,7 +355,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -369,7 +369,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -383,7 +383,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -397,7 +397,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -411,7 +411,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
},
@@ -425,7 +425,7 @@
"str x20, [x28, #24]",
"mov w1, #0x401",
"str x1, [x28, #1328]",
"ldr x0, [x28, #2336]",
"ldr x0, [x28, #2680]",
"br x0"
]
}
unittests/InstructionCountCI/AVX128/VEX_map1.json
+32 -32
View File
@@ -485,7 +485,7 @@
],
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2560]",
"ldr q3, [x28, #2896]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -499,7 +499,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ushr v3.4s, v16.4s, #31",
"ldr q4, [x28, #2560]",
"ldr q4, [x28, #2896]",
"ushl v3.4s, v3.4s, v4.4s",
"addv s3, v3.4s",
"mov w20, v3.s[0]",
@@ -1122,7 +1122,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1134,7 +1134,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1146,7 +1146,7 @@
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1171,7 +1171,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1185,7 +1185,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1199,7 +1199,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1223,7 +1223,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1235,7 +1235,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1247,7 +1247,7 @@
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1274,7 +1274,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1288,7 +1288,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1302,7 +1302,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1326,7 +1326,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1338,7 +1338,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1350,7 +1350,7 @@
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -1377,7 +1377,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1391,7 +1391,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q3, [x0, #32]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -1405,7 +1405,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q3, [x0, #48]",
"tbl v16.16b, {v17.16b}, v3.16b",
"tbl v2.16b, {v2.16b}, v3.16b",
@@ -2288,7 +2288,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -2302,7 +2302,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q4, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2315,7 +2315,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -2329,7 +2329,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q4, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2342,7 +2342,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
@@ -2356,7 +2356,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q4, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
"tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -3763,7 +3763,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d",
"stp xzr, xzr, [x28, #32]"
@@ -3777,7 +3777,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr q4, [x28, #2464]",
"ldr q4, [x28, #2800]",
"eor v5.16b, v18.16b, v4.16b",
"fadd v16.2d, v17.2d, v5.2d",
"eor v3.16b, v3.16b, v4.16b",
@@ -3791,7 +3791,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s",
"stp xzr, xzr, [x28, #32]"
@@ -3805,7 +3805,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"ldr q3, [x28, #64]",
"ldr q4, [x28, #2432]",
"ldr q4, [x28, #2768]",
"eor v5.16b, v18.16b, v4.16b",
"fadd v16.4s, v17.4s, v5.4s",
"eor v3.16b, v3.16b, v4.16b",
@@ -3976,7 +3976,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #3024]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@@ -3992,7 +3992,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"ldr q3, [x28, #2688]",
"ldr q3, [x28, #3024]",
"cmlt v4.16b, v16.16b, #0",
"and v4.16b, v4.16b, v3.16b",
"addp v4.16b, v4.16b, v4.16b",
unittests/InstructionCountCI/AVX128/VEX_map2.json
+25 -25
View File
@@ -1917,7 +1917,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2400]",
"ldr q2, [x28, #2736]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -4485,7 +4485,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4502,7 +4502,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2432]",
"ldr q5, [x28, #2768]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4518,7 +4518,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -4535,7 +4535,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2464]",
"ldr q5, [x28, #2800]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -4551,7 +4551,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4568,7 +4568,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2496]",
"ldr q5, [x28, #2832]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -4584,7 +4584,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -4601,7 +4601,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2528]",
"ldr q5, [x28, #2864]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -5541,7 +5541,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5558,7 +5558,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2432]",
"ldr q5, [x28, #2768]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5574,7 +5574,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5591,7 +5591,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2464]",
"ldr q5, [x28, #2800]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5607,7 +5607,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5624,7 +5624,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2496]",
"ldr q5, [x28, #2832]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -5640,7 +5640,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5657,7 +5657,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2528]",
"ldr q5, [x28, #2864]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -5673,7 +5673,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5689,7 +5689,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2432]",
"ldr q5, [x28, #2768]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5704,7 +5704,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -5720,7 +5720,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2464]",
"ldr q5, [x28, #2800]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -5735,7 +5735,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5751,7 +5751,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2496]",
"ldr q5, [x28, #2832]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -5766,7 +5766,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -5782,7 +5782,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2528]",
"ldr q5, [x28, #2864]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+24 -24
View File
@@ -2843,7 +2843,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2860,7 +2860,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2432]",
"ldr q5, [x28, #2768]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2876,7 +2876,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -2893,7 +2893,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2464]",
"ldr q5, [x28, #2800]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -2909,7 +2909,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2926,7 +2926,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2496]",
"ldr q5, [x28, #2832]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
@@ -2942,7 +2942,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -2959,7 +2959,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2528]",
"ldr q5, [x28, #2864]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
@@ -3879,7 +3879,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -3896,7 +3896,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2432]",
"ldr q5, [x28, #2768]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -3912,7 +3912,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -3929,7 +3929,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2464]",
"ldr q5, [x28, #2800]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -3945,7 +3945,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -3962,7 +3962,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2496]",
"ldr q5, [x28, #2832]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
@@ -3978,7 +3978,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -3995,7 +3995,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2528]",
"ldr q5, [x28, #2864]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
@@ -4011,7 +4011,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4027,7 +4027,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2432]",
"ldr q5, [x28, #2768]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4042,7 +4042,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -4058,7 +4058,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2464]",
"ldr q5, [x28, #2800]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -4073,7 +4073,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4089,7 +4089,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2496]",
"ldr q5, [x28, #2832]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
@@ -4104,7 +4104,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
@@ -4120,7 +4120,7 @@
"ldr q2, [x28, #32]",
"ldr q3, [x28, #48]",
"ldr q4, [x28, #64]",
"ldr q5, [x28, #2528]",
"ldr q5, [x28, #2864]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
unittests/InstructionCountCI/AVX128/VEX_map3.json
+8 -8
View File
@@ -337,7 +337,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2592]",
"ldr q2, [x28, #2928]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
]
@@ -348,7 +348,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2608]",
"ldr q2, [x28, #2944]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
]
@@ -369,7 +369,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2624]",
"ldr q2, [x28, #2960]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
]
@@ -391,7 +391,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2976]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
]
@@ -412,7 +412,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2656]",
"ldr q2, [x28, #2992]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
]
@@ -423,7 +423,7 @@
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #3008]",
"tbx v16.16b, {v17.16b}, v2.16b",
"stp xzr, xzr, [x28, #32]"
]
@@ -3488,7 +3488,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr q3, [x28, #2576]",
"ldr q3, [x28, #2912]",
"mov v16.16b, v17.16b",
"aese v16.16b, v2.16b",
"tbl v16.16b, {v16.16b}, v3.16b",
@@ -3502,7 +3502,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldr q3, [x28, #2576]",
"ldr q3, [x28, #2912]",
"mov v16.16b, v17.16b",
"aese v16.16b, v2.16b",
"tbl v16.16b, {v16.16b}, v3.16b",
unittests/InstructionCountCI/Crypto/H0F38.json
+1 -1
View File
@@ -31,7 +31,7 @@
"0x66 0x0f 0x38 0xca"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q2, [x0, #432]",
"tbl v3.16b, {v16.16b}, v2.16b",
"tbl v4.16b, {v17.16b}, v2.16b",
unittests/InstructionCountCI/Crypto/H0F3A.json
+10 -10
View File
@@ -55,7 +55,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"ldr q2, [x28, #2912]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"aese v16.16b, v3.16b",
@@ -68,7 +68,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"ldr q2, [x28, #2912]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"aese v16.16b, v3.16b",
@@ -84,9 +84,9 @@
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2960]",
"ldr q2, [x28, #3296]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -101,9 +101,9 @@
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2976]",
"ldr q2, [x28, #3312]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -118,9 +118,9 @@
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2992]",
"ldr q2, [x28, #3328]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
@@ -135,9 +135,9 @@
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3008]",
"ldr q2, [x28, #3344]",
"movi v3.2d, #0x0",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q4, [x0, #432]",
"tbl v5.16b, {v16.16b}, v4.16b",
"tbl v6.16b, {v17.16b}, v4.16b",
unittests/InstructionCountCI/FlagM/HotBlocks.json
+5 -22
View File
@@ -900,37 +900,20 @@
]
},
"pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 19,
"Comment": [
"A Hat In Time spends at least 5% CPU time in this instruction",
"Comes from vcruntime140.dll wcsstr"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"str x8, [x28, #320]",
"stp x16, x17, [x28, #384]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"stp x18, x30, [x0], #16",
"str x30, [sp, #-16]!",
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0xd",
"ldr x1, [x28, #1760]",
"ldr x1, [x28, #2096]",
"ldr x3, [x28, #2104]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x7, [x28, #288]",
"ldp x5, x6, [x28, #304]",
"ldr x8, [x28, #320]",
"ldp x16, x17, [x28, #384]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldp x18, x30, [sp], #16",
"ldr x30, [sp], #16",
"mov w20, w0",
"mov w27, #0x0",
"uxth w21, w20",
unittests/InstructionCountCI/FlagM/Secondary.json
+1 -1
View File
@@ -1604,7 +1604,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #2688]",
"ldr d3, [x28, #3024]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+1 -1
View File
@@ -37,7 +37,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #3024]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/FlagM/VEX_map1.json
+2 -2
View File
@@ -68,7 +68,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #3024]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@@ -83,7 +83,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1912]",
"ldr x0, [x28, #2256]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json
+4806 -23065
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+973 -4602
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+11652 -55618
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+14630 -70148
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+1843 -7752
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+209 -1143
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/H0F38.json
+1 -1
View File
@@ -685,7 +685,7 @@
"0x66 0x0f 0x38 0x41"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2400]",
"ldr q2, [x28, #2736]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
unittests/InstructionCountCI/H0F3A.json
+7 -7
View File
@@ -327,7 +327,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2592]",
"ldr q2, [x28, #2928]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -337,7 +337,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2608]",
"ldr q2, [x28, #2944]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -356,7 +356,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2624]",
"ldr q2, [x28, #2960]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -376,7 +376,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2640]",
"ldr q2, [x28, #2976]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -395,7 +395,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2656]",
"ldr q2, [x28, #2992]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -405,7 +405,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2672]",
"ldr q2, [x28, #3008]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -474,7 +474,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2128]",
"ldr x0, [x28, #2472]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/PrimaryGroup.json
+4 -4
View File
@@ -2825,7 +2825,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #3056]",
"ldr x3, [x28, #3392]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2836,7 +2836,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #3072]",
"ldr x3, [x28, #3408]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2894,7 +2894,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #3064]",
"ldr x3, [x28, #3400]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
@@ -2907,7 +2907,7 @@
"mov x0, x5",
"mov x1, x4",
"mov x2, x6",
"ldr x3, [x28, #3080]",
"ldr x3, [x28, #3416]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
unittests/InstructionCountCI/SSE42_Strings.json
+22 -90
View File
@@ -36,38 +36,21 @@
},
"Instructions": {
"pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 34,
"ExpectedInstructionCount": 17,
"Comment": [
"0x66 0x0f 0x3A 0x60"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2080]",
"ldr x0, [x28, #2088]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
"mrs x2, nzcv",
"str w2, [x28, #1000]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"str x8, [x28, #320]",
"stp x16, x17, [x28, #384]",
"sub sp, sp, #0x70 (112)",
"mov x2, sp",
"st1 {v2.2d, v3.2d}, [x2], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x2], #64",
"stp x18, x30, [x2], #16",
"mov w2, #0x0",
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w2, #0x0",
"ldr x3, [x28, #1752]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x7, [x28, #288]",
"ldp x5, x6, [x28, #304]",
"ldr x8, [x28, #320]",
"ldp x16, x17, [x28, #384]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldp x18, x30, [sp], #16",
"ldp xzr, x30, [sp], #16",
"mov w20, w0",
"mov w27, #0x0",
"uxth w0, w20",
@@ -78,38 +61,21 @@
]
},
"pcmpestri xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 38,
"ExpectedInstructionCount": 21,
"Comment": [
"0x66 0x0f 0x3A 0x61"
],
"ExpectedArm64ASM": [
"ldr x3, [x28, #2080]",
"ldr x0, [x28, #2088]",
"stp x0, x30, [sp, #-16]!",
"mov x0, x4",
"mov x1, x5",
"mrs x2, nzcv",
"str w2, [x28, #1000]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"str x8, [x28, #320]",
"stp x16, x17, [x28, #384]",
"sub sp, sp, #0x70 (112)",
"mov x2, sp",
"st1 {v2.2d, v3.2d}, [x2], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x2], #64",
"stp x18, x30, [x2], #16",
"mov w2, #0x0",
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w2, #0x0",
"ldr x3, [x28, #1752]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x7, [x28, #288]",
"ldp x5, x6, [x28, #304]",
"ldr x8, [x28, #320]",
"ldp x16, x17, [x28, #384]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldp x18, x30, [sp], #16",
"ldp xzr, x30, [sp], #16",
"mov w20, w0",
"mov w27, #0x0",
"uxth w21, w20",
@@ -124,36 +90,19 @@
]
},
"pcmpistrm xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 32,
"ExpectedInstructionCount": 15,
"Comment": [
"0x66 0x0f 0x3A 0x62"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"str x8, [x28, #320]",
"stp x16, x17, [x28, #384]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"stp x18, x30, [x0], #16",
"str x30, [sp, #-16]!",
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x0",
"ldr x1, [x28, #1760]",
"ldr x1, [x28, #2096]",
"ldr x3, [x28, #2104]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x7, [x28, #288]",
"ldp x5, x6, [x28, #304]",
"ldr x8, [x28, #320]",
"ldp x16, x17, [x28, #384]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldp x18, x30, [sp], #16",
"ldr x30, [sp], #16",
"mov w20, w0",
"mov w27, #0x0",
"uxth w0, w20",
@@ -164,36 +113,19 @@
]
},
"pcmpistri xmm0, xmm1, 0_0_00_00_00b": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 19,
"Comment": [
"0x66 0x0f 0x3A 0x63"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x7, [x28, #288]",
"stp x5, x6, [x28, #304]",
"str x8, [x28, #320]",
"stp x16, x17, [x28, #384]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"stp x18, x30, [x0], #16",
"str x30, [sp, #-16]!",
"mov v0.16b, v16.16b",
"mov v1.16b, v17.16b",
"mov w0, #0x0",
"ldr x1, [x28, #1760]",
"ldr x1, [x28, #2096]",
"ldr x3, [x28, #2104]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x7, [x28, #288]",
"ldp x5, x6, [x28, #304]",
"ldr x8, [x28, #320]",
"ldp x16, x17, [x28, #384]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldp x18, x30, [sp], #16",
"ldr x30, [sp], #16",
"mov w20, w0",
"mov w27, #0x0",
"uxth w21, w20",
unittests/InstructionCountCI/Secondary.json
+8 -8
View File
@@ -648,7 +648,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2560]",
"ldr q3, [x28, #2896]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -659,7 +659,7 @@
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2560]",
"ldr q3, [x28, #2896]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
@@ -1154,7 +1154,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1056]",
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"strb wzr, [x28, #1019]",
@@ -1169,7 +1169,7 @@
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"strb wzr, [x28, #1019]",
@@ -3512,7 +3512,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
]
@@ -3521,7 +3521,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #16]",
"mov v0.16b, v17.16b",
"mov v1.16b, v16.16b",
@@ -3533,7 +3533,7 @@
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q3, [x0, #16]",
"mov v0.16b, v16.16b",
"mov v1.16b, v2.16b",
@@ -3651,7 +3651,7 @@
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"ldr d3, [x28, #2688]",
"ldr d3, [x28, #3024]",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/Secondary_OpSize.json
+5 -5
View File
@@ -522,7 +522,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -536,7 +536,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -674,7 +674,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #2096]",
"ldr x0, [x28, #2440]",
"ldr q3, [x0, #2480]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -1226,7 +1226,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
@@ -1282,7 +1282,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0x66 0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #3024]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
unittests/InstructionCountCI/Secondary_REP.json
+12 -12
View File
@@ -117,7 +117,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2816]",
"ldr s2, [x28, #3152]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
@@ -131,7 +131,7 @@
"ldr s2, [x6]",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"ldr s3, [x28, #3152]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -144,7 +144,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2848]",
"ldr s2, [x28, #3184]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
@@ -158,7 +158,7 @@
"ldr d2, [x6]",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"ldr s3, [x28, #3184]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -172,7 +172,7 @@
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"ldr s3, [x28, #3152]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -187,7 +187,7 @@
"frinti s2, s2",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"ldr s3, [x28, #3152]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -201,7 +201,7 @@
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"ldr s3, [x28, #3184]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -216,7 +216,7 @@
"frinti s2, s2",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"ldr s3, [x28, #3184]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -295,8 +295,8 @@
"ExpectedInstructionCount": 6,
"Comment": "0xf3 0x0f 0x5b",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr q3, [x28, #2816]",
"ldr q2, [x28, #3248]",
"ldr q3, [x28, #3152]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
@@ -396,7 +396,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -409,7 +409,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2088]",
"ldr x0, [x28, #2432]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
unittests/InstructionCountCI/Secondary_REPNE.json
+3 -3
View File
@@ -290,7 +290,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q2, [x0, #1280]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -303,7 +303,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2080]",
"ldr x0, [x28, #2424]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -459,7 +459,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]
unittests/InstructionCountCI/VEX_map1.json
+33 -33
View File
@@ -2802,7 +2802,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2871,7 +2871,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2940,7 +2940,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2104]",
"ldr x0, [x28, #2448]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -3285,7 +3285,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, s16",
"mov w21, #0x80000000",
"ldr s2, [x28, #2816]",
"ldr s2, [x28, #3152]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel w4, w20, w21, gt",
@@ -3300,7 +3300,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, s16",
"mov x21, #0x8000000000000000",
"ldr s2, [x28, #2848]",
"ldr s2, [x28, #3184]",
"mrs x22, nzcv",
"fcmp s2, s16",
"csel x4, x20, x21, gt",
@@ -3315,7 +3315,7 @@
"ExpectedArm64ASM": [
"fcvtzs w20, d16",
"mov w21, #0x80000000",
"ldr d2, [x28, #2864]",
"ldr d2, [x28, #3200]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel w4, w20, w21, gt",
@@ -3330,7 +3330,7 @@
"ExpectedArm64ASM": [
"fcvtzs x20, d16",
"mov x21, #0x8000000000000000",
"ldr d2, [x28, #2896]",
"ldr d2, [x28, #3232]",
"mrs x22, nzcv",
"fcmp d2, d16",
"csel x4, x20, x21, gt",
@@ -3346,7 +3346,7 @@
"frinti s2, s16",
"fcvtzs w20, s2",
"mov w21, #0x80000000",
"ldr s3, [x28, #2816]",
"ldr s3, [x28, #3152]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel w4, w20, w21, gt",
@@ -3362,7 +3362,7 @@
"frinti s2, s16",
"fcvtzs x20, s2",
"mov x21, #0x8000000000000000",
"ldr s3, [x28, #2848]",
"ldr s3, [x28, #3184]",
"mrs x22, nzcv",
"fcmp s3, s2",
"csel x4, x20, x21, gt",
@@ -3378,7 +3378,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"ldr d3, [x28, #3232]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -3394,7 +3394,7 @@
"frinti d2, d16",
"fcvtzs x20, d2",
"mov x21, #0x8000000000000000",
"ldr d3, [x28, #2896]",
"ldr d3, [x28, #3232]",
"mrs x22, nzcv",
"fcmp d3, d2",
"csel x4, x20, x21, gt",
@@ -3657,8 +3657,8 @@
],
"ExpectedArm64ASM": [
"frinti v2.4s, v17.4s",
"ldr q3, [x28, #2912]",
"ldr q4, [x28, #2816]",
"ldr q3, [x28, #3248]",
"ldr q4, [x28, #3152]",
"fcvtzs v5.4s, v2.4s",
"fcmgt v2.4s, v4.4s, v2.4s",
"mov v16.16b, v2.16b",
@@ -3672,9 +3672,9 @@
],
"ExpectedArm64ASM": [
"frinti z2.s, p7/m, z17.s",
"ldr x0, [x28, #2024]",
"ldr x0, [x28, #2368]",
"ld1b {z3.b}, p7/z, [x0]",
"ldr x0, [x28, #1976]",
"ldr x0, [x28, #2320]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.s",
"fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -3692,8 +3692,8 @@
"Map 1 0b10 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr q3, [x28, #2816]",
"ldr q2, [x28, #3248]",
"ldr q3, [x28, #3152]",
"fcvtzs v4.4s, v17.4s",
"fcmgt v3.4s, v3.4s, v17.4s",
"mov v16.16b, v3.16b",
@@ -3706,9 +3706,9 @@
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2024]",
"ldr x0, [x28, #2368]",
"ld1b {z2.b}, p7/z, [x0]",
"ldr x0, [x28, #1976]",
"ldr x0, [x28, #2320]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.s",
"fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -4441,7 +4441,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
@@ -4452,7 +4452,7 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1800]",
"ldr x0, [x28, #2144]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
@@ -4464,7 +4464,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
@@ -4475,7 +4475,7 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1784]",
"ldr x0, [x28, #2128]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
@@ -4601,7 +4601,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2688]",
"ldr q2, [x28, #3024]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
@@ -4616,7 +4616,7 @@
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1912]",
"ldr x0, [x28, #2256]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
@@ -4993,8 +4993,8 @@
"Map 1 0b01 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #2912]",
"ldr q3, [x28, #2864]",
"ldr d2, [x28, #3248]",
"ldr q3, [x28, #3200]",
"fcvtzs z4.s, p6/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
"mov v4.8b, v4.8b",
@@ -5010,8 +5010,8 @@
"Map 1 0b01 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr x0, [x28, #2000]",
"ldr q2, [x28, #3248]",
"ldr x0, [x28, #2344]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
@@ -5054,8 +5054,8 @@
],
"ExpectedArm64ASM": [
"frinti v2.2d, v17.2d",
"ldr d3, [x28, #2912]",
"ldr q4, [x28, #2864]",
"ldr d3, [x28, #3248]",
"ldr q4, [x28, #3200]",
"fcvtzs z5.s, p6/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
"mov v5.8b, v5.8b",
@@ -5072,8 +5072,8 @@
],
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #2912]",
"ldr x0, [x28, #2000]",
"ldr q3, [x28, #3248]",
"ldr x0, [x28, #2344]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+8 -8
View File
@@ -112,9 +112,9 @@
],
"ExpectedArm64ASM": [
"frinti z2.s, p7/m, z17.s",
"ldr x0, [x28, #2024]",
"ldr x0, [x28, #2368]",
"ld1b {z3.b}, p7/z, [x0]",
"ldr x0, [x28, #1976]",
"ldr x0, [x28, #2320]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.s",
"fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -142,9 +142,9 @@
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2024]",
"ldr x0, [x28, #2368]",
"ld1b {z2.b}, p7/z, [x0]",
"ldr x0, [x28, #1976]",
"ldr x0, [x28, #2320]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.s",
"fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -173,8 +173,8 @@
"Map 1 0b01 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2912]",
"ldr x0, [x28, #2000]",
"ldr q2, [x28, #3248]",
"ldr x0, [x28, #2344]",
"ld1b {z3.b}, p7/z, [x0]",
"fcvtzs z4.s, p7/m, z17.d",
"uzp1 z4.s, z4.s, z4.s",
@@ -208,8 +208,8 @@
],
"ExpectedArm64ASM": [
"frinti z2.d, p7/m, z17.d",
"ldr q3, [x28, #2912]",
"ldr x0, [x28, #2000]",
"ldr q3, [x28, #3248]",
"ldr x0, [x28, #2344]",
"ld1b {z4.b}, p7/z, [x0]",
"fcvtzs z5.s, p7/m, z2.d",
"uzp1 z5.s, z5.s, z5.s",
unittests/InstructionCountCI/VEX_map2.json
+25 -25
View File
@@ -1603,7 +1603,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2400]",
"ldr q2, [x28, #2736]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -3657,7 +3657,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.4s, v16.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -3669,7 +3669,7 @@
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1784]",
"ldr x0, [x28, #2128]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3683,7 +3683,7 @@
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.2d, v16.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -3695,7 +3695,7 @@
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1800]",
"ldr x0, [x28, #2144]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3709,7 +3709,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.4s, v16.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -3721,7 +3721,7 @@
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1816]",
"ldr x0, [x28, #2160]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -3735,7 +3735,7 @@
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v17.16b, v2.16b",
"fmla v2.2d, v16.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -3747,7 +3747,7 @@
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1832]",
"ldr x0, [x28, #2176]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z17.d, z2.d",
"mov z0.d, z2.d",
@@ -4609,7 +4609,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.4s, v17.4s, v16.4s",
"mov v16.16b, v2.16b"
@@ -4621,7 +4621,7 @@
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1784]",
"ldr x0, [x28, #2128]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4635,7 +4635,7 @@
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.2d, v17.2d, v16.2d",
"mov v16.16b, v2.16b"
@@ -4647,7 +4647,7 @@
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1800]",
"ldr x0, [x28, #2144]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4661,7 +4661,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.4s, v17.4s, v16.4s",
"mov v16.16b, v2.16b"
@@ -4673,7 +4673,7 @@
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1816]",
"ldr x0, [x28, #2160]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4687,7 +4687,7 @@
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v18.16b, v2.16b",
"fmla v2.2d, v17.2d, v16.2d",
"mov v16.16b, v2.16b"
@@ -4699,7 +4699,7 @@
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1832]",
"ldr x0, [x28, #2176]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"mov z0.d, z2.d",
@@ -4713,7 +4713,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2432]",
"ldr q2, [x28, #2768]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.4s, v17.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -4725,7 +4725,7 @@
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1784]",
"ldr x0, [x28, #2128]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4738,7 +4738,7 @@
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2464]",
"ldr q2, [x28, #2800]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.2d, v17.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -4750,7 +4750,7 @@
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1800]",
"ldr x0, [x28, #2144]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4763,7 +4763,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2496]",
"ldr q2, [x28, #2832]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.4s, v17.4s, v18.4s",
"mov v16.16b, v2.16b"
@@ -4775,7 +4775,7 @@
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1816]",
"ldr x0, [x28, #2160]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
@@ -4788,7 +4788,7 @@
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"ldr q2, [x28, #2864]",
"eor v2.16b, v16.16b, v2.16b",
"fmla v2.2d, v17.2d, v18.2d",
"mov v16.16b, v2.16b"
@@ -4800,7 +4800,7 @@
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1832]",
"ldr x0, [x28, #2176]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z16.d, z2.d",
"mov z16.d, z2.d",
unittests/InstructionCountCI/VEX_map3.json
+2 -2
View File
@@ -5372,7 +5372,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"ldr q2, [x28, #2912]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"aese v16.16b, v3.16b",
@@ -5385,7 +5385,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"ldr q2, [x28, #2912]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"aese v16.16b, v3.16b",
unittests/InstructionCountCI/x87.json
+1822 -7655
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64.json
+209 -1143
View File
File diff suppressed because it is too large. Load diff