mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-24 23:00:44 +02:00
Adds new vector ops to the interpreter
This commit is contained in:
Ryan Houdek committed
1 parent
a8d4d0d3c3
commit
3cd1e0ee8f
1 file changed
+260
-38
@@ -1999,6 +1999,17 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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} \
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break; \
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}
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#define DO_VECTOR_PAIR_OP(size, type, func) \
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case size: { \
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auto *Dst_d = reinterpret_cast<type*>(Tmp); \
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auto *Src1_d = reinterpret_cast<type*>(Src1); \
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auto *Src2_d = reinterpret_cast<type*>(Src2); \
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for (uint8_t i = 0; i < Elements; ++i) { \
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Dst_d[i] = func(Src1_d[i*2], Src1_d[i*2 + 1]); \
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Dst_d[i+Elements] = func(Src2_d[i*2], Src2_d[i*2 + 1]); \
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} \
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break; \
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}
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#define DO_VECTOR_SCALAR_OP(size, type, func)\
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case size: { \
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auto *Dst_d = reinterpret_cast<type*>(Tmp); \
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@@ -2201,6 +2212,35 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VSQSUB: {
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auto Op = IROp->C<IR::IROp_VSQSub>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t Tmp[16];
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto b) {
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__int128_t res = a - b;
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if (res < std::numeric_limits<decltype(a)>::min())
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return std::numeric_limits<decltype(a)>::min();
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if (res > std::numeric_limits<decltype(a)>::max())
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return std::numeric_limits<decltype(a)>::max();
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return (decltype(a))res;
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};
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switch (Op->ElementSize) {
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DO_VECTOR_OP(1, int8_t, Func)
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DO_VECTOR_OP(2, int16_t, Func)
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DO_VECTOR_OP(4, int32_t, Func)
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DO_VECTOR_OP(8, int64_t, Func)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VFADD: {
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auto Op = IROp->C<IR::IROp_VFAdd>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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@@ -2235,6 +2275,25 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VADDP: {
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auto Op = IROp->C<IR::IROp_VAddP>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t Tmp[16];
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto b) { return a + b; };
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switch (Op->ElementSize) {
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DO_VECTOR_PAIR_OP(1, uint8_t, Func)
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DO_VECTOR_PAIR_OP(2, uint16_t, Func)
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DO_VECTOR_PAIR_OP(4, uint32_t, Func)
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DO_VECTOR_PAIR_OP(8, uint64_t, Func)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VFMUL: {
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auto Op = IROp->C<IR::IROp_VFMul>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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@@ -2351,22 +2410,32 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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#define DO_VECTOR_1SRC_2TYPE_OP(size, type, type2, func, max) \
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#define DO_VECTOR_1SRC_2TYPE_OP(size, type, type2, func, min, max) \
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case size: { \
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auto *Dst_d = reinterpret_cast<type*>(Tmp); \
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auto *Src_d = reinterpret_cast<type2*>(Src); \
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for (uint8_t i = 0; i < Elements; ++i) { \
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Dst_d[i] = (type)func(Src_d[i], max); \
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Dst_d[i] = (type)func(Src_d[i], min, max); \
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} \
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break; \
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}
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#define DO_VECTOR_1SRC_2TYPE_OP_TOP(size, type, type2, func, max) \
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#define DO_VECTOR_1SRC_2TYPE_OP_TOP(size, type, type2, func, min, max) \
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case size: { \
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auto *Dst_d = reinterpret_cast<type*>(Tmp); \
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auto *Src_d = reinterpret_cast<type2*>(Src2); \
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memcpy(Dst_d, Src1, Elements * sizeof(type2));\
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for (uint8_t i = 0; i < Elements; ++i) { \
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Dst_d[i+Elements] = (type)func(Src_d[i], max); \
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Dst_d[i+Elements] = (type)func(Src_d[i], min, max); \
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} \
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break; \
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}
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#define DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(size, type, type2, func, min, max) \
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case size: { \
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auto *Dst_d = reinterpret_cast<type*>(Tmp); \
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auto *Src_d = reinterpret_cast<type2*>(Src); \
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for (uint8_t i = 0; i < Elements; ++i) { \
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Dst_d[i] = (type)func(Src_d[i+Elements], min, max); \
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} \
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break; \
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}
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@@ -2380,18 +2449,98 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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} \
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break; \
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}
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#define DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(size, type, type2, func) \
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case size: { \
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auto *Dst_d = reinterpret_cast<type*>(Tmp); \
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auto *Src1_d = reinterpret_cast<type2*>(Src1); \
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auto *Src2_d = reinterpret_cast<type2*>(Src2); \
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for (uint8_t i = 0; i < Elements; ++i) { \
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Dst_d[i] = (type)func((type)Src1_d[i+Elements], (type)Src2_d[i+Elements]); \
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} \
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break; \
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}
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case IR::OP_VSQXTUN: {
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auto Op = IROp->C<IR::IROp_VSQXTUN>();
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case IR::OP_VUSHRNI: {
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auto Op = IROp->C<IR::IROp_VUShrNI>();
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void *Src = GetSrc<void*>(Op->Header.Args[0]);
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uint8_t BitShift = Op->BitShift;
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uint8_t Tmp[16]{};
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [BitShift](auto a, auto min, auto max) { return BitShift >= (sizeof(a) * 8) ? 0 : a >> BitShift; };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(2, uint8_t, uint16_t, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP(4, uint16_t, uint32_t, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, uint32_t, uint64_t, Func, 0, 0)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VUSHRNI2: {
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auto Op = IROp->C<IR::IROp_VUShrNI2>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t BitShift = Op->BitShift;
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uint8_t Tmp[16];
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto max) { return std::max(std::min(a, (decltype(a))max), (decltype(a))0); };
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auto Func = [BitShift](auto a, auto min, auto max) { return BitShift >= (sizeof(a) * 8) ? 0 : a >> BitShift; };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(2, uint8_t, int16_t, Func, (1 << 8) - 1)
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DO_VECTOR_1SRC_2TYPE_OP(4, uint16_t, int32_t, Func, (1 << 16) - 1)
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DO_VECTOR_1SRC_2TYPE_OP_TOP(2, uint8_t, uint16_t, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP_TOP(4, uint16_t, uint32_t, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP_TOP(8, uint32_t, uint64_t, Func, 0, 0)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VSQXTN: {
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auto Op = IROp->C<IR::IROp_VSQXTN>();
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void *Src = GetSrc<void*>(Op->Header.Args[0]);
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uint8_t Tmp[16]{};
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto min, auto max) { return std::max(std::min(a, (decltype(a))max), (decltype(a))min); };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(2, int8_t, int16_t, Func, std::numeric_limits<int8_t>::min(), std::numeric_limits<int8_t>::max())
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DO_VECTOR_1SRC_2TYPE_OP(4, int16_t, int32_t, Func, std::numeric_limits<int16_t>::min(), std::numeric_limits<int16_t>::max())
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VSQXTN2: {
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auto Op = IROp->C<IR::IROp_VSQXTN2>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t Tmp[16]{};
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto min, auto max) { return std::max(std::min(a, (decltype(a))max), (decltype(a))min); };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP_TOP(2, int8_t, int16_t, Func, std::numeric_limits<int8_t>::min(), std::numeric_limits<int8_t>::max())
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DO_VECTOR_1SRC_2TYPE_OP_TOP(4, int16_t, int32_t, Func, std::numeric_limits<int16_t>::min(), std::numeric_limits<int16_t>::max())
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VSQXTUN: {
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auto Op = IROp->C<IR::IROp_VSQXTUN>();
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void *Src = GetSrc<void*>(Op->Header.Args[0]);
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uint8_t Tmp[16]{};
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto min, auto max) { return std::max(std::min(a, (decltype(a))max), (decltype(a))min); };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(2, uint8_t, int16_t, Func, 0, (1 << 8) - 1)
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DO_VECTOR_1SRC_2TYPE_OP(4, uint16_t, int32_t, Func, 0, (1 << 16) - 1)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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@@ -2401,14 +2550,14 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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auto Op = IROp->C<IR::IROp_VSQXTUN2>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t Tmp[16];
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uint8_t Tmp[16]{};
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto max) { return std::max(std::min(a, (decltype(a))max), (decltype(a))0); };
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auto Func = [](auto a, auto min, auto max) { return std::max(std::min(a, (decltype(a))max), (decltype(a))min); };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP_TOP(2, uint8_t, int16_t, Func, (1 << 8) - 1)
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DO_VECTOR_1SRC_2TYPE_OP_TOP(4, uint16_t, int32_t, Func, (1 << 16) - 1)
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DO_VECTOR_1SRC_2TYPE_OP_TOP(2, uint8_t, int16_t, Func, 0, (1 << 8) - 1)
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DO_VECTOR_1SRC_2TYPE_OP_TOP(4, uint16_t, int32_t, Func, 0, (1 << 16) - 1)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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@@ -2421,10 +2570,10 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto max) { return a; };
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auto Func = [](auto a, auto min, auto max) { return a; };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(4, float, uint32_t, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, double, uint64_t, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(4, float, uint32_t, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, double, uint64_t, Func, 0, 0)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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@@ -2437,10 +2586,10 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto max) { return a; };
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auto Func = [](auto a, auto min, auto max) { return a; };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(4, float, int32_t, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, double, int64_t, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(4, float, int32_t, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, double, int64_t, Func, 0, 0)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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@@ -2453,10 +2602,10 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto max) { return a; };
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auto Func = [](auto a, auto min, auto max) { return a; };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(4, uint32_t, float, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, uint64_t, double, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(4, uint32_t, float, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, uint64_t, double, Func, 0, 0)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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@@ -2469,10 +2618,10 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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uint8_t Elements = Op->RegisterSize / Op->ElementSize;
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auto Func = [](auto a, auto max) { return a; };
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auto Func = [](auto a, auto min, auto max) { return a; };
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switch (Op->ElementSize) {
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DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0)
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DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
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DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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@@ -2554,18 +2703,73 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VUMULL2: {
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auto Op = IROp->C<IR::IROp_VUMull2>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t Tmp[16];
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uint8_t Elements = Op->RegisterSize / (Op->ElementSize << 1);
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auto Func = [](auto a, auto b) { return a * b; };
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switch (Op->ElementSize) {
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DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(1, uint16_t, uint8_t, Func)
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DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(2, uint32_t, uint16_t, Func)
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DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(4, uint64_t, uint32_t, Func)
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default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
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}
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memcpy(GDP, Tmp, Op->RegisterSize);
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break;
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}
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case IR::OP_VSMULL2: {
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auto Op = IROp->C<IR::IROp_VSMull2>();
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void *Src1 = GetSrc<void*>(Op->Header.Args[0]);
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void *Src2 = GetSrc<void*>(Op->Header.Args[1]);
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uint8_t Tmp[16];
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uint8_t Elements = Op->RegisterSize / (Op->ElementSize << 1);
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auto Func = [](auto a, auto b) { return a * b; };
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switch (Op->ElementSize) {
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DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(1, int16_t, int8_t, Func)
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DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(2, int32_t, int16_t, Func)
|
||||
DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(4, int64_t, int32_t, Func)
|
||||
default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
|
||||
}
|
||||
memcpy(GDP, Tmp, Op->RegisterSize);
|
||||
break;
|
||||
}
|
||||
case IR::OP_VSXTL: {
|
||||
auto Op = IROp->C<IR::IROp_VSXTL>();
|
||||
void *Src = GetSrc<void*>(Op->Header.Args[0]);
|
||||
uint8_t Tmp[16];
|
||||
uint8_t Tmp[16]{};
|
||||
|
||||
uint8_t Elements = Op->RegisterSize / Op->ElementSize;
|
||||
|
||||
auto Func = [](auto a, auto max) { return a; };
|
||||
auto Func = [](auto a, auto min, auto max) { return a; };
|
||||
switch (Op->ElementSize) {
|
||||
DO_VECTOR_1SRC_2TYPE_OP(1, int16_t, int8_t, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(2, int32_t, int16_t, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(4, int64_t, int32_t, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(1, int16_t, int8_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(2, int32_t, int16_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(4, int64_t, int32_t, Func, 0, 0)
|
||||
default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
|
||||
}
|
||||
memcpy(GDP, Tmp, Op->RegisterSize);
|
||||
break;
|
||||
}
|
||||
case IR::OP_VSXTL2: {
|
||||
auto Op = IROp->C<IR::IROp_VSXTL2>();
|
||||
void *Src = GetSrc<void*>(Op->Header.Args[0]);
|
||||
uint8_t Tmp[16];
|
||||
|
||||
uint8_t Elements = Op->RegisterSize / (Op->ElementSize << 1);
|
||||
|
||||
auto Func = [](auto a, auto min, auto max) { return a; };
|
||||
switch (Op->ElementSize) {
|
||||
DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(1, int16_t, int8_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(2, int32_t, int16_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(4, int64_t, int32_t, Func, 0, 0)
|
||||
default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
|
||||
}
|
||||
memcpy(GDP, Tmp, Op->RegisterSize);
|
||||
@@ -2574,15 +2778,33 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
|
||||
case IR::OP_VUXTL: {
|
||||
auto Op = IROp->C<IR::IROp_VUXTL>();
|
||||
void *Src = GetSrc<void*>(Op->Header.Args[0]);
|
||||
uint8_t Tmp[16];
|
||||
uint8_t Tmp[16]{};
|
||||
|
||||
uint8_t Elements = Op->RegisterSize / Op->ElementSize;
|
||||
|
||||
auto Func = [](auto a, auto max) { return a; };
|
||||
auto Func = [](auto a, auto min, auto max) { return a; };
|
||||
switch (Op->ElementSize) {
|
||||
DO_VECTOR_1SRC_2TYPE_OP(1, uint16_t, uint8_t, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(2, uint32_t, uint16_t, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(4, uint64_t, uint32_t, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(1, uint16_t, uint8_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(2, uint32_t, uint16_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(4, uint64_t, uint32_t, Func, 0, 0)
|
||||
default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
|
||||
}
|
||||
memcpy(GDP, Tmp, Op->RegisterSize);
|
||||
break;
|
||||
}
|
||||
case IR::OP_VUXTL2: {
|
||||
auto Op = IROp->C<IR::IROp_VUXTL2>();
|
||||
void *Src = GetSrc<void*>(Op->Header.Args[0]);
|
||||
|
||||
uint8_t Tmp[16];
|
||||
|
||||
uint8_t Elements = Op->RegisterSize / (Op->ElementSize << 1);
|
||||
|
||||
auto Func = [](auto a, auto min, auto max) { return a; };
|
||||
switch (Op->ElementSize) {
|
||||
DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(1, uint16_t, uint8_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(2, uint32_t, uint16_t, Func, 0, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(4, uint64_t, uint32_t, Func, 0, 0)
|
||||
default: LogMan::Msg::A("Unknown Element Size: %d", Op->ElementSize); break;
|
||||
}
|
||||
memcpy(GDP, Tmp, Op->RegisterSize);
|
||||
@@ -3221,19 +3443,19 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
|
||||
|
||||
uint16_t Conv = (Op->DstElementSize << 8) | Op->SrcElementSize;
|
||||
|
||||
auto Func = [](auto a, auto max) { return a; };
|
||||
auto Func = [](auto a, auto min, auto max) { return a; };
|
||||
switch (Conv) {
|
||||
case 0x0804: { // Double <- float
|
||||
uint8_t Elements = Op->RegisterSize / Op->SrcElementSize;
|
||||
switch (Op->SrcElementSize) {
|
||||
DO_VECTOR_1SRC_2TYPE_OP(4, double, float, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(4, double, float, Func, 0, 0)
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 0x0408: { // Float <- Double
|
||||
uint8_t Elements = Op->RegisterSize / Op->SrcElementSize;
|
||||
switch (Op->SrcElementSize) {
|
||||
DO_VECTOR_1SRC_2TYPE_OP(8, float, double, Func, 0)
|
||||
DO_VECTOR_1SRC_2TYPE_OP(8, float, double, Func, 0, 0)
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
Reference in new issue
Block a user