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ARMEmitter: Handle SVE saturating inc/dec register by element count
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@@ -1118,7 +1118,105 @@ public:
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}
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// SVE saturating inc/dec register by element count
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// XXX:
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void sqincb(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1100, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqincb(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1100, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqincb(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1101, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqincb(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1101, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdecb(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1110, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdecb(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1110, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdecb(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1111, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdecb(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1111, SubRegSize::i8Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqinch(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1100, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqinch(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1100, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqinch(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1101, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqinch(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1101, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdech(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1110, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdech(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1110, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdech(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1111, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdech(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1111, SubRegSize::i16Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqincw(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1100, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqincw(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1100, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqincw(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1101, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqincw(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1101, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdecw(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1110, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdecw(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1110, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdecw(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1111, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdecw(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1111, SubRegSize::i32Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqincd(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1100, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqincd(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1100, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqincd(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1101, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqincd(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1101, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdecd(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1110, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void sqdecd(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1110, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdecd(XRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(1, 0b1111, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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void uqdecd(WRegister rdn, PredicatePattern pattern, uint32_t imm) {
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SVEElementCount(0, 0b1111, SubRegSize::i64Bit, ZRegister{rdn.Idx()}, pattern, imm);
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}
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// SVE Bitwise Immediate
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// XXX: DUPM
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+127
-1
@@ -1195,7 +1195,133 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE inc/dec register by elemen
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE saturating inc/dec register by element count") {
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// TODO: Implement in emitter.
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TEST_SINGLE(sqincb(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqincb x30, pow2");
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TEST_SINGLE(sqincb(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqincb x30, vl256, mul #7");
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TEST_SINGLE(sqincb(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqincb x30, all, mul #16");
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TEST_SINGLE(sqincb(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqincb x30, w30, pow2");
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TEST_SINGLE(sqincb(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqincb x30, w30, vl256, mul #7");
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TEST_SINGLE(sqincb(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqincb x30, w30, all, mul #16");
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TEST_SINGLE(uqincb(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqincb x30, pow2");
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TEST_SINGLE(uqincb(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqincb x30, vl256, mul #7");
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TEST_SINGLE(uqincb(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqincb x30, all, mul #16");
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TEST_SINGLE(uqincb(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqincb w30, pow2");
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TEST_SINGLE(uqincb(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqincb w30, vl256, mul #7");
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TEST_SINGLE(uqincb(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqincb w30, all, mul #16");
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TEST_SINGLE(sqdecb(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqdecb x30, pow2");
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TEST_SINGLE(sqdecb(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqdecb x30, vl256, mul #7");
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TEST_SINGLE(sqdecb(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqdecb x30, all, mul #16");
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TEST_SINGLE(sqdecb(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqdecb x30, w30, pow2");
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TEST_SINGLE(sqdecb(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqdecb x30, w30, vl256, mul #7");
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TEST_SINGLE(sqdecb(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqdecb x30, w30, all, mul #16");
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TEST_SINGLE(uqdecb(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqdecb x30, pow2");
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TEST_SINGLE(uqdecb(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqdecb x30, vl256, mul #7");
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TEST_SINGLE(uqdecb(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqdecb x30, all, mul #16");
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TEST_SINGLE(uqdecb(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqdecb w30, pow2");
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TEST_SINGLE(uqdecb(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqdecb w30, vl256, mul #7");
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TEST_SINGLE(uqdecb(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqdecb w30, all, mul #16");
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TEST_SINGLE(sqinch(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqinch x30, pow2");
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TEST_SINGLE(sqinch(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqinch x30, vl256, mul #7");
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TEST_SINGLE(sqinch(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqinch x30, all, mul #16");
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TEST_SINGLE(sqinch(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqinch x30, w30, pow2");
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TEST_SINGLE(sqinch(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqinch x30, w30, vl256, mul #7");
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TEST_SINGLE(sqinch(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqinch x30, w30, all, mul #16");
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TEST_SINGLE(uqinch(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqinch x30, pow2");
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TEST_SINGLE(uqinch(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqinch x30, vl256, mul #7");
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TEST_SINGLE(uqinch(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqinch x30, all, mul #16");
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TEST_SINGLE(uqinch(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqinch w30, pow2");
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TEST_SINGLE(uqinch(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqinch w30, vl256, mul #7");
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TEST_SINGLE(uqinch(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqinch w30, all, mul #16");
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TEST_SINGLE(sqdech(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqdech x30, pow2");
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TEST_SINGLE(sqdech(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqdech x30, vl256, mul #7");
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TEST_SINGLE(sqdech(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqdech x30, all, mul #16");
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TEST_SINGLE(sqdech(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqdech x30, w30, pow2");
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TEST_SINGLE(sqdech(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqdech x30, w30, vl256, mul #7");
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TEST_SINGLE(sqdech(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqdech x30, w30, all, mul #16");
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TEST_SINGLE(uqdech(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqdech x30, pow2");
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TEST_SINGLE(uqdech(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqdech x30, vl256, mul #7");
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TEST_SINGLE(uqdech(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqdech x30, all, mul #16");
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TEST_SINGLE(uqdech(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqdech w30, pow2");
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TEST_SINGLE(uqdech(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqdech w30, vl256, mul #7");
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TEST_SINGLE(uqdech(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqdech w30, all, mul #16");
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TEST_SINGLE(sqincw(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqincw x30, pow2");
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TEST_SINGLE(sqincw(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqincw x30, vl256, mul #7");
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TEST_SINGLE(sqincw(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqincw x30, all, mul #16");
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TEST_SINGLE(sqincw(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqincw x30, w30, pow2");
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TEST_SINGLE(sqincw(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqincw x30, w30, vl256, mul #7");
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TEST_SINGLE(sqincw(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqincw x30, w30, all, mul #16");
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TEST_SINGLE(uqincw(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqincw x30, pow2");
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TEST_SINGLE(uqincw(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqincw x30, vl256, mul #7");
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TEST_SINGLE(uqincw(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqincw x30, all, mul #16");
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TEST_SINGLE(uqincw(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqincw w30, pow2");
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TEST_SINGLE(uqincw(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqincw w30, vl256, mul #7");
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TEST_SINGLE(uqincw(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqincw w30, all, mul #16");
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TEST_SINGLE(sqdecw(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqdecw x30, pow2");
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TEST_SINGLE(sqdecw(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqdecw x30, vl256, mul #7");
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TEST_SINGLE(sqdecw(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqdecw x30, all, mul #16");
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TEST_SINGLE(sqdecw(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqdecw x30, w30, pow2");
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TEST_SINGLE(sqdecw(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqdecw x30, w30, vl256, mul #7");
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TEST_SINGLE(sqdecw(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqdecw x30, w30, all, mul #16");
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TEST_SINGLE(uqdecw(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqdecw x30, pow2");
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TEST_SINGLE(uqdecw(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqdecw x30, vl256, mul #7");
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TEST_SINGLE(uqdecw(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqdecw x30, all, mul #16");
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TEST_SINGLE(uqdecw(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqdecw w30, pow2");
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TEST_SINGLE(uqdecw(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqdecw w30, vl256, mul #7");
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TEST_SINGLE(uqdecw(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqdecw w30, all, mul #16");
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TEST_SINGLE(sqincd(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqincd x30, pow2");
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TEST_SINGLE(sqincd(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqincd x30, vl256, mul #7");
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TEST_SINGLE(sqincd(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqincd x30, all, mul #16");
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TEST_SINGLE(sqincd(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqincd x30, w30, pow2");
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TEST_SINGLE(sqincd(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqincd x30, w30, vl256, mul #7");
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TEST_SINGLE(sqincd(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqincd x30, w30, all, mul #16");
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TEST_SINGLE(uqincd(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqincd x30, pow2");
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TEST_SINGLE(uqincd(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqincd x30, vl256, mul #7");
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TEST_SINGLE(uqincd(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqincd x30, all, mul #16");
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TEST_SINGLE(uqincd(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqincd w30, pow2");
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TEST_SINGLE(uqincd(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqincd w30, vl256, mul #7");
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TEST_SINGLE(uqincd(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqincd w30, all, mul #16");
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TEST_SINGLE(sqdecd(XReg::x30, PredicatePattern::SVE_POW2 , 1), "sqdecd x30, pow2");
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TEST_SINGLE(sqdecd(XReg::x30, PredicatePattern::SVE_VL256, 7), "sqdecd x30, vl256, mul #7");
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TEST_SINGLE(sqdecd(XReg::x30, PredicatePattern::SVE_ALL , 16), "sqdecd x30, all, mul #16");
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TEST_SINGLE(sqdecd(WReg::w30, PredicatePattern::SVE_POW2 , 1), "sqdecd x30, w30, pow2");
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TEST_SINGLE(sqdecd(WReg::w30, PredicatePattern::SVE_VL256, 7), "sqdecd x30, w30, vl256, mul #7");
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TEST_SINGLE(sqdecd(WReg::w30, PredicatePattern::SVE_ALL , 16), "sqdecd x30, w30, all, mul #16");
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TEST_SINGLE(uqdecd(XReg::x30, PredicatePattern::SVE_POW2 , 1), "uqdecd x30, pow2");
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TEST_SINGLE(uqdecd(XReg::x30, PredicatePattern::SVE_VL256, 7), "uqdecd x30, vl256, mul #7");
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TEST_SINGLE(uqdecd(XReg::x30, PredicatePattern::SVE_ALL , 16), "uqdecd x30, all, mul #16");
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TEST_SINGLE(uqdecd(WReg::w30, PredicatePattern::SVE_POW2 , 1), "uqdecd w30, pow2");
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TEST_SINGLE(uqdecd(WReg::w30, PredicatePattern::SVE_VL256, 7), "uqdecd w30, vl256, mul #7");
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TEST_SINGLE(uqdecd(WReg::w30, PredicatePattern::SVE_ALL , 16), "uqdecd w30, all, mul #16");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE Bitwise Immediate") {
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