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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed 2024-01-30 22:26:59 -04:00
1 parent 0bc9e1a409
commit 4cc59ba8f5
4 files changed
+36 -62
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unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+8 -16
View File
@@ -1113,16 +1113,14 @@
]
},
"shr al, 2": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC0 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w26, w20, #2",
"bfxil x4, x26, #0, #8",
"cset w21, vs",
"cmn wzr, w26, lsl #24",
"rmif x20, #0, #nzCv",
"rmif x21, #0, #nzcV"
"rmif x20, #0, #nzCv"
]
},
"sar al, 2": {
@@ -1331,42 +1329,36 @@
]
},
"shr ax, 2": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w26, w20, #2",
"bfxil x4, x26, #0, #16",
"cset w21, vs",
"cmn wzr, w26, lsl #16",
"rmif x20, #0, #nzCv",
"rmif x21, #0, #nzcV"
"rmif x20, #0, #nzCv"
]
},
"shr eax, 2": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsr w4, w20, #2",
"cset w21, vs",
"tst w4, w4",
"rmif x20, #0, #nzCv",
"mov x26, x4",
"rmif x21, #0, #nzcV"
"mov x26, x4"
]
},
"shr rax, 2": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"lsr x4, x20, #2",
"cset w21, vs",
"tst x4, x4",
"rmif x20, #0, #nzCv",
"mov x26, x4",
"rmif x21, #0, #nzcV"
"mov x26, x4"
]
},
"sar ax, 2": {
unittests/InstructionCountCI/FlagM/Secondary.json
+8 -13
View File
@@ -779,13 +779,12 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"and x22, x5, #0x1f",
"mov w23, #0x10",
"sub x23, x23, x22",
"lsl x24, x21, x22",
@@ -809,15 +808,13 @@
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 22,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x20",
"sub x23, x23, x22",
"and x22, x5, #0x1f",
"neg x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
@@ -839,14 +836,12 @@
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
"uxtb w21, w5",
"and x21, x21, #0x3f",
"mov w22, #0x40",
"sub x22, x22, x21",
"and x21, x5, #0x3f",
"neg x22, x21",
"lsl x23, x20, x21",
"lsr x22, x7, x22",
"orr x22, x23, x22",
unittests/InstructionCountCI/PrimaryGroup.json
+12 -20
View File
@@ -1239,18 +1239,16 @@
]
},
"shr al, 2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xC0 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w26, w20, #2",
"bfxil x4, x26, #0, #8",
"cset w21, vs",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"mrs x21, nzcv",
"ubfx x20, x20, #1, #1",
"orr w20, w22, w20, lsl #29",
"orr w20, w20, w21, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
@@ -1508,50 +1506,44 @@
]
},
"shr ax, 2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w26, w20, #2",
"bfxil x4, x26, #0, #16",
"cset w21, vs",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"mrs x21, nzcv",
"ubfx x20, x20, #1, #1",
"orr w20, w22, w20, lsl #29",
"orr w20, w20, w21, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"shr eax, 2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsr w4, w20, #2",
"cset w21, vs",
"tst w4, w4",
"mrs x22, nzcv",
"mrs x21, nzcv",
"ubfx x20, x20, #1, #1",
"orr w20, w22, w20, lsl #29",
"orr w20, w21, w20, lsl #29",
"mov x26, x4",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"shr rax, 2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"lsr x4, x20, #2",
"cset w21, vs",
"tst x4, x4",
"mrs x22, nzcv",
"mrs x21, nzcv",
"ubfx x20, x20, #1, #1",
"orr w20, w22, w20, lsl #29",
"orr w20, w21, w20, lsl #29",
"mov x26, x4",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
unittests/InstructionCountCI/Secondary.json
+8 -13
View File
@@ -1593,13 +1593,12 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 27,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"and x22, x5, #0x1f",
"mov w23, #0x10",
"sub x23, x23, x22",
"lsl x24, x21, x22",
@@ -1627,15 +1626,13 @@
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x20",
"sub x23, x23, x22",
"and x22, x5, #0x1f",
"neg x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
@@ -1661,14 +1658,12 @@
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 24,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
"uxtb w21, w5",
"and x21, x21, #0x3f",
"mov w22, #0x40",
"sub x22, x22, x21",
"and x21, x5, #0x3f",
"neg x22, x21",
"lsl x23, x20, x21",
"lsr x22, x7, x22",
"orr x22, x23, x22",