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VURAvg: Fix arm64 jit

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Stefanos Kornilios Mitsis Poiitidis committed 2020-07-04 21:52:15 +03:00
1 parent 8eaa11f4f2
commit 560d467058
2 files changed
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External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
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@@ -340,6 +340,7 @@ private:
DEF_OP(VSQSub);
DEF_OP(VAddP);
DEF_OP(VAddV);
DEF_OP(VURAvg);
DEF_OP(VAbs);
DEF_OP(VFAdd);
DEF_OP(VFAddP);
External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
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@@ -1875,6 +1875,7 @@ void JITCore::RegisterVectorHandlers() {
REGISTER_OP(VSQSUB, VSQSub);
REGISTER_OP(VADDP, VAddP);
REGISTER_OP(VADDV, VAddV);
REGISTER_OP(VURAVG, VURAvg);
REGISTER_OP(VABS, VAbs);
REGISTER_OP(VFADD, VFAdd);
REGISTER_OP(VFADDP, VFAddP);