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Merge pull request #446 from Sonicadvance1/umul_fix

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Fixes unsigned multiply zext mechanics
This commit is contained in:
Stefanos Kornilios Mitsis Poiitidis authored and GitHub committed 2020-09-30 19:49:49 +03:00
2 parents 81a03d67d9 6af0bace1a
commit 56f47395db
3 files changed
+29 -6
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External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+6 -5
View File
@@ -2615,6 +2615,8 @@ void OpDispatchBuilder::IMULOp(OpcodeArgs) {
void OpDispatchBuilder::MULOp(OpcodeArgs) {
uint8_t Size = GetSrcSize(Op);
uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4;
OrderedNode *Src1 = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src2 = _LoadContext(Size, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RAX]), GPRClass);
if (Size != 8) {
@@ -2639,11 +2641,10 @@ void OpDispatchBuilder::MULOp(OpcodeArgs) {
else if (Size == 4) {
// 32bits stored in EAX
// 32bits stored in EDX
OrderedNode *ResultLow = _Bfe(32, 0, Result);
ResultHigh = _Bfe(32, 32, Result);
_StoreContext(GPRClass, 4, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RAX]), ResultLow);
_StoreContext(GPRClass, 4, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDX]), ResultHigh);
OrderedNode *ResultLow = _Bfe(GPRSize, 32, 0, Result);
ResultHigh = _Bfe(GPRSize, 32, 32, Result);
_StoreContext(GPRClass, GPRSize, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RAX]), ResultLow);
_StoreContext(GPRClass, GPRSize, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RDX]), ResultHigh);
}
else if (Size == 8) {
LogMan::Throw::A(CTX->Config.Is64BitMode, "Doesn't exist in 32bit mode");
unittests/ASM/PrimaryGroup/3_F6_04.asm
+8 -1
View File
@@ -1,7 +1,8 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x414243444546008E"
"RAX": "0x414243444546008E",
"RBX": "0xFFFFFFFFFFFF0004"
},
"MemoryRegions": {
"0x100000000": "4096"
@@ -20,6 +21,12 @@ mov al, 2
mul byte [rdx + 8 * 0 + 1]
mov word [rdx + 8 * 0], ax
; Ensure this inserts in to AX
mov rax, 0xFFFFFFFFFFFFFF02
mov rbx, 0xFFFFFFFFFFFFFF02
mul bl
mov rbx, rax
mov rax, [rdx + 8 * 0]
hlt
unittests/ASM/PrimaryGroup/3_F7_04.asm
+15
View File
@@ -3,6 +3,8 @@
"RegData": {
"RAX": "0x414243441F968610",
"RBX": "0x25D1437D318C1BE0",
"RCX": "0xFFFFFFFFFFFF0004",
"RDX": "0x0000000000000004",
"RSI": "0xFC1B5FC85401D0C0",
"RSP": "0x2B27F79B13618682"
},
@@ -36,6 +38,19 @@ mul qword [r15 + 8 * 2 + 0]
mov rsi, rax
mov rsp, rdx
; Ensure zext handling is correct
; 16bit
mov rax, 0xFFFFFFFFFFFF0002
mov rbx, 0xFFFFFFFFFFFF0002
mul bx
mov rcx, rax
; 32bit
mov rax, 0xFFFFFFFF00000002
mov rbx, 0xFFFFFFFF00000002
mul ebx
mov rdx, rax
mov rax, [r15 + 8 * 0]
mov rbx, [r15 + 8 * 1]