OpcodeDispatcher: Implement SHA1MSG2

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -5277,6 +5277,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
   constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> H0F38_SHA1[] = {
     {OPD(PF_38_NONE, 0xC8), 1, &OpDispatchBuilder::SHA1NEXTEOp},
     {OPD(PF_38_NONE, 0xC9), 1, &OpDispatchBuilder::SHA1MSG1Op},
+    {OPD(PF_38_NONE, 0xCA), 1, &OpDispatchBuilder::SHA1MSG2Op},
   };
 
   constexpr std::tuple<uint16_t, uint8_t, FEXCore::X86Tables::OpDispatchPtr> H0F38_AES[] = {

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -591,6 +591,7 @@ public:
 
   void SHA1NEXTEOp(OpcodeArgs);
   void SHA1MSG1Op(OpcodeArgs);
+  void SHA1MSG2Op(OpcodeArgs);
 
   void AESImcOp(OpcodeArgs);
   void AESEncOp(OpcodeArgs);

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -47,6 +47,29 @@ void OpDispatchBuilder::SHA1MSG1Op(OpcodeArgs) {
   StoreResult(FPRClass, Op, D0, -1);
 }
 
+void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+
+  // ROR by 31 is equivalent to a ROL by 1
+  auto ThirtyOne = _Constant(32, 31);
+
+  auto W13 = _VExtractToGPR(16, 4, Src, 2);
+  auto W14 = _VExtractToGPR(16, 4, Src, 1);
+  auto W15 = _VExtractToGPR(16, 4, Src, 0);
+  auto W16 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 3), W13), ThirtyOne);
+  auto W17 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 2), W14), ThirtyOne);
+  auto W18 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 1), W15), ThirtyOne);
+  auto W19 = _Ror(_Xor(_VExtractToGPR(16, 4, Dest, 0), W16), ThirtyOne);
+
+  auto D3 = _VInsGPR(16, 4, 3, Dest, W16);
+  auto D2 = _VInsGPR(16, 4, 2, D3, W17);
+  auto D1 = _VInsGPR(16, 4, 1, D2, W18);
+  auto D0 = _VInsGPR(16, 4, 0, D1, W19);
+
+  StoreResult(FPRClass, Op, D0, -1);
+}
+
 void OpDispatchBuilder::AESImcOp(OpcodeArgs) {
   OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
   auto Res = _VAESImc(Src);

External/FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp

@@ -89,6 +89,7 @@ void InitializeH0F38Tables() {
 
     {OPD(PF_38_NONE, 0xC8), 1, X86InstInfo{"SHA1NEXTE",  TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_NONE, 0xC9), 1, X86InstInfo{"SHA1MSG1",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_NONE, 0xCA), 1, X86InstInfo{"SHA1MSG2",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(PF_38_66,   0xDB), 1, X86InstInfo{"AESIMC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_66,   0xDC), 1, X86InstInfo{"AESENC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},

unittests/ASM/H0F38/sha1msg2.asm

@@ -0,0 +1,22 @@
+%ifdef CONFIG
+{
+  "RegData": {
+      "XMM1": ["0x1B0233CC7FCDBB45", "0x1ECD2142EC058BF8"],
+      "XMM2": ["0x6868C3F3AAED56E0", "0xF0FCE9E294E6E6DE"]
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+movaps xmm1, [rdx + 16 * 0]
+movaps xmm2, [rdx + 16 * 1]
+
+sha1msg2 xmm1, xmm2
+
+hlt
+
+align 16
+.data:
+db 0xe0, 0xfc, 0x2b, 0xa1, 0x06, 0x4f, 0x6c, 0xa7, 0x0f, 0x06, 0x6a, 0x1e, 0x7f, 0x76, 0x80, 0x9b
+db 0xe0, 0x56, 0xed, 0xaa, 0xf3, 0xc3, 0x68, 0x68, 0xde, 0xe6, 0xe6, 0x94, 0xe2, 0xe9, 0xfc, 0xf0