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https://github.com/FEX-Emu/FEX.git
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Merge pull request #2502 from lioncash/flag
OpcodeDispatcher: Handle VPINSRB/VPINSRD/VPINSRQ/VPINSRW
This commit is contained in:
9 files changed
+297
-37
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+19
-13
@@ -304,18 +304,19 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
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(Options.w && CTX->Config.Is64BitMode);
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const bool HasNarrowingDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0;
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bool HasXMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
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!HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
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!HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_SRC);
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bool HasXMMDst = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
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!HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_GPR) &&
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!HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_DST);
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bool HasMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
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!HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
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HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_SRC);
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bool HasMMDst = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
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!HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_GPR) &&
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HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_DST);
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const bool HasXMMFlags = (Info->Flags & InstFlags::FLAGS_XMM_FLAGS) != 0;
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bool HasXMMSrc = HasXMMFlags &&
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!HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_SRC_GPR) &&
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!HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_SRC);
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bool HasXMMDst = HasXMMFlags &&
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!HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_DST_GPR) &&
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!HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_DST);
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bool HasMMSrc = HasXMMFlags &&
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!HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_SRC_GPR) &&
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HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_SRC);
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bool HasMMDst = HasXMMFlags &&
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!HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_DST_GPR) &&
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HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_DST);
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// Is ModRM present via explicit instruction encoded or REX?
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const bool HasMODRM = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM);
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@@ -502,7 +503,12 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
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if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_VEX_1ST_SRC) != 0) {
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DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
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DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
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DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMSrc);
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// If we have XMM flags at all, then SRC 1 cannot be a GPR. The only case where
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// this is possible is with BMI1 and BMI2 instructions (which are all GPR-based
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// and don't use XMM flags)
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DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMFlags);
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++CurrentSrc;
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}
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@@ -5788,6 +5788,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
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{OPD(1, 0b10, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<4, true>},
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{OPD(1, 0b11, 0xC2), 1, &OpDispatchBuilder::AVXVFCMPOp<8, true>},
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{OPD(1, 0b01, 0xC4), 1, &OpDispatchBuilder::VPINSRWOp},
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{OPD(1, 0b01, 0xC5), 1, &OpDispatchBuilder::PExtrOp<2>},
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{OPD(1, 0b00, 0xC6), 1, &OpDispatchBuilder::VSHUFOp<4>},
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@@ -5949,8 +5950,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
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{OPD(3, 0b01, 0x18), 1, &OpDispatchBuilder::VINSERTOp},
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{OPD(3, 0b01, 0x19), 1, &OpDispatchBuilder::VEXTRACT128Op},
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{OPD(3, 0b01, 0x20), 1, &OpDispatchBuilder::VPINSRBOp},
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{OPD(3, 0b01, 0x21), 1, &OpDispatchBuilder::VINSERTPSOp},
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{OPD(3, 0b01, 0x22), 1, &OpDispatchBuilder::VPINSRDQOp},
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{OPD(3, 0b01, 0x38), 1, &OpDispatchBuilder::VINSERTOp},
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{OPD(3, 0b01, 0x39), 1, &OpDispatchBuilder::VEXTRACT128Op},
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@@ -496,6 +496,10 @@ public:
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void VPHSUBOp(OpcodeArgs);
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void VPHSUBSWOp(OpcodeArgs);
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void VPINSRBOp(OpcodeArgs);
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void VPINSRDQOp(OpcodeArgs);
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void VPINSRWOp(OpcodeArgs);
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void VPMADDUBSWOp(OpcodeArgs);
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void VPMADDWDOp(OpcodeArgs);
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@@ -840,6 +844,11 @@ private:
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OrderedNode* PHSUBSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1Op,
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const X86Tables::DecodedOperand& Src2Op);
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OrderedNode* PINSROpImpl(OpcodeArgs, size_t ElementSize,
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const X86Tables::DecodedOperand& Src1Op,
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const X86Tables::DecodedOperand& Src2Op,
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const X86Tables::DecodedOperand& Imm);
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OrderedNode* PMADDWDOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
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const X86Tables::DecodedOperand& Src2);
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@@ -1287,28 +1287,32 @@ void OpDispatchBuilder::VBROADCASTOp<8>(OpcodeArgs);
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template
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void OpDispatchBuilder::VBROADCASTOp<16>(OpcodeArgs);
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OrderedNode* OpDispatchBuilder::PINSROpImpl(OpcodeArgs, size_t ElementSize,
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const X86Tables::DecodedOperand& Src1Op,
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const X86Tables::DecodedOperand& Src2Op,
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const X86Tables::DecodedOperand& Imm) {
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const auto Size = GetDstSize(Op);
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const auto NumElements = Size / ElementSize;
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OrderedNode *Src2{};
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if (Src2Op.IsGPR()) {
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Src2 = LoadSource(GPRClass, Op, Src2Op, Op->Flags, -1);
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} else {
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// If loading from memory then we only load the element size
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Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, ElementSize, Op->Flags, -1);
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}
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OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, Size, Op->Flags, -1);
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LOGMAN_THROW_A_FMT(Imm.IsLiteral(), "Imm needs to be literal here");
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const uint64_t Index = Imm.Data.Literal.Value & (NumElements - 1);
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return _VInsGPR(Size, ElementSize, Index, Src1, Src2);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PINSROp(OpcodeArgs) {
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auto Size = GetDstSize(Op);
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OrderedNode *Src{};
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if (Op->Src[0].IsGPR()) {
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Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
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}
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else {
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// If loading from memory then we only load the element size
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Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], ElementSize, Op->Flags, -1);
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}
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OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetDstSize(Op), Op->Flags, -1);
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LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
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uint64_t Index = Op->Src[1].Data.Literal.Value;
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uint8_t NumElements = Size / ElementSize;
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Index &= NumElements - 1;
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// This maps 1:1 to an AArch64 NEON Op
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auto ALUOp = _VInsGPR(Size, ElementSize, Index, Dest, Src);
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StoreResult(FPRClass, Op, ALUOp, -1);
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OrderedNode *Result = PINSROpImpl(Op, ElementSize, Op->Dest, Op->Src[0], Op->Src[1]);
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StoreResult(FPRClass, Op, Result, -1);
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}
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template
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@@ -1320,6 +1324,28 @@ void OpDispatchBuilder::PINSROp<4>(OpcodeArgs);
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template
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void OpDispatchBuilder::PINSROp<8>(OpcodeArgs);
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void OpDispatchBuilder::VPINSRBOp(OpcodeArgs) {
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OrderedNode *Result = PINSROpImpl(Op, 1, Op->Src[0], Op->Src[1], Op->Src[2]);
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OrderedNode *Final = _VMov(16, Result);
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StoreResult(FPRClass, Op, Final, -1);
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}
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void OpDispatchBuilder::VPINSRDQOp(OpcodeArgs) {
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const auto SrcSize = GetSrcSize(Op);
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OrderedNode *Result = PINSROpImpl(Op, SrcSize, Op->Src[0], Op->Src[1], Op->Src[2]);
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OrderedNode *Final = _VMov(16, Result);
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StoreResult(FPRClass, Op, Final, -1);
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}
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void OpDispatchBuilder::VPINSRWOp(OpcodeArgs) {
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OrderedNode *Result = PINSROpImpl(Op, 2, Op->Src[0], Op->Src[1], Op->Src[2]);
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OrderedNode *Final = _VMov(16, Result);
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StoreResult(FPRClass, Op, Final, -1);
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}
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OrderedNode* OpDispatchBuilder::InsertPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
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const X86Tables::DecodedOperand& Src2,
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const X86Tables::DecodedOperand& Imm) {
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@@ -102,7 +102,7 @@ void InitializeVEXTables() {
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{OPD(1, 0b10, 0xC2), 1, X86InstInfo{"VCMPccSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(1, 0b11, 0xC2), 1, X86InstInfo{"VCMPccSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(1, 0b01, 0xC4), 1, X86InstInfo{"VPINSRW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(1, 0b01, 0xC4), 1, X86InstInfo{"VPINSRW", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_SF_SRC_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(1, 0b01, 0xC5), 1, X86InstInfo{"VPEXTRW", TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(1, 0b00, 0xC6), 1, X86InstInfo{"VSHUFPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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@@ -430,9 +430,9 @@ void InitializeVEXTables() {
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{OPD(3, 0b01, 0x19), 1, X86InstInfo{"VEXTRACTF128", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_256BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x1D), 1, X86InstInfo{"VCVTPS2PH", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x20), 1, X86InstInfo{"VPINSRB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x20), 1, X86InstInfo{"VPINSRB", TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, nullptr}},
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{OPD(3, 0b01, 0x21), 1, X86InstInfo{"VINSERTPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x22), 1, X86InstInfo{"VPINSRD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
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{OPD(3, 0b01, 0x22), 1, X86InstInfo{"VPINSR{D,Q}", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, nullptr}},
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{OPD(3, 0b01, 0x38), 1, X86InstInfo{"VINSERTI128", TYPE_INST, GenFlagsSameSize(SIZE_256BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 1, nullptr}},
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{OPD(3, 0b01, 0x39), 1, X86InstInfo{"VEXTRACTI128", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_256BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
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@@ -0,0 +1,62 @@
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%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM3": ["0x48510F254D2FA47F", "0x2B5774313A974886", "0x0000000000000000", "0x0000000000000000"],
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"XMM4": ["0x006B6B6B6B6B6B6B", "0x6B00000000000000", "0x0000000000000000", "0x0000000000000000"]
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}
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}
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%endif
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lea rdx, [rel .data]
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vpxor xmm2, xmm2, xmm2
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vpinsrb xmm3, xmm1, [rdx + 8 * 0 + 0], 0x00
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 1], 0x01
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 2], 0x02
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 3], 0x03
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 4], 0x04
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 5], 0x05
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 6], 0x06
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vpinsrb xmm3, xmm3, [rdx + 8 * 0 + 7], 0x07
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 0], 0x08
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 1], 0x09
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 2], 0x0A
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 3], 0x0B
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 4], 0x0C
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 5], 0x0D
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 6], 0x0E
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vpinsrb xmm3, xmm3, [rdx + 8 * 1 + 7], 0x0F
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vpinsrb xmm4, xmm2, [rdx + 8 * 2 + 0], 0xFF
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mov rax, [rdx + 16]
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vpinsrb xmm4, xmm4, eax, 0x00
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vpinsrb xmm4, xmm4, eax, 0x01
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vpinsrb xmm4, xmm4, eax, 0x02
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vpinsrb xmm4, xmm4, eax, 0x03
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vpinsrb xmm4, xmm4, eax, 0x04
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vpinsrb xmm4, xmm4, eax, 0x05
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vpinsrb xmm4, xmm4, eax, 0x06
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hlt
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align 32
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; 256bytes of random data
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.data:
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db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b
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db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67
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db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7
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db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a
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db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19
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db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9
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db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2
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db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4
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db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c
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db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76
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db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca
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db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65
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db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10
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db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e
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db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07
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db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09
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@@ -0,0 +1,50 @@
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%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM1": ["0xB615B9533DE8AD09", "0xB76472A37404B890", "0x24426B4C72F110AD", "0x8A6789F2D415A567"],
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"XMM2": ["0x48510F254D2FA47F", "0x2B5774313A974886", "0x0000000000000000", "0x0000000000000000"],
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"XMM3": ["0x3DE8AD093DE8AD09", "0x3DE8AD093DE8AD09", "0x0000000000000000", "0x0000000000000000"],
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"XMM4": ["0x0000000000000000", "0x1F6DE86B00000000", "0x0000000000000000", "0x0000000000000000"]
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}
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}
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%endif
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||||
|
||||
lea rdx, [rel .data]
|
||||
|
||||
vpxor xmm4, xmm4, xmm4
|
||||
vmovaps ymm1, [rdx + 32]
|
||||
|
||||
vpinsrd xmm2, xmm1, [rdx + 0], 0x00
|
||||
vpinsrd xmm2, xmm2, [rdx + 4], 0x01
|
||||
vpinsrd xmm2, xmm2, [rdx + 8], 0x02
|
||||
vpinsrd xmm2, xmm2, [rdx + 12], 0x03
|
||||
vpinsrd xmm4, xmm4, [rdx + 16], 0xFF
|
||||
mov rax, [rdx + 32]
|
||||
|
||||
vpinsrd xmm3, xmm3, eax, 0x00
|
||||
vpinsrd xmm3, xmm3, eax, 0x01
|
||||
vpinsrd xmm3, xmm3, eax, 0x02
|
||||
vpinsrd xmm3, xmm3, eax, 0x03
|
||||
|
||||
hlt
|
||||
|
||||
align 32
|
||||
; 256bytes of random data
|
||||
.data:
|
||||
db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b
|
||||
db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67
|
||||
db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7
|
||||
db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a
|
||||
db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19
|
||||
db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9
|
||||
db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2
|
||||
db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4
|
||||
db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c
|
||||
db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76
|
||||
db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca
|
||||
db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65
|
||||
db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10
|
||||
db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e
|
||||
db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07
|
||||
db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09
|
||||
@@ -0,0 +1,46 @@
|
||||
%ifdef CONFIG
|
||||
{
|
||||
"HostFeatures": ["AVX"],
|
||||
"RegData": {
|
||||
"XMM1": ["0x8996F88178236612", "0x19A26B823D3CA2A9", "0x00F658AB689712B0", "0xC97D9D031ED21972"],
|
||||
"XMM2": ["0x0000000000000000", "0xB615B9533DE8AD09", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM3": ["0x8996F88178236612", "0x8996F88178236612", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM4": ["0x48510F254D2FA47F", "0x2B5774313A974886", "0x0000000000000000", "0x0000000000000000"]
|
||||
}
|
||||
}
|
||||
%endif
|
||||
|
||||
lea rdx, [rel .data]
|
||||
|
||||
vpxor xmm2, xmm2, xmm2
|
||||
vmovaps ymm1, [rdx + 64]
|
||||
|
||||
vpinsrq xmm4, xmm1, [rdx + 0], 0x00
|
||||
vpinsrq xmm4, xmm4, [rdx + 8], 0x01
|
||||
vpinsrq xmm2, xmm2, [rdx + 32], 0xFF
|
||||
mov rax, [rdx + 64]
|
||||
|
||||
vpinsrq xmm3, xmm3, rax, 0x00
|
||||
vpinsrq xmm3, xmm3, rax, 0x01
|
||||
|
||||
hlt
|
||||
|
||||
align 32
|
||||
; 256bytes of random data
|
||||
.data:
|
||||
db 0x7f, 0xa4, 0x2f, 0x4d, 0x25, 0x0f, 0x51, 0x48, 0x86, 0x48, 0x97, 0x3a, 0x31, 0x74, 0x57, 0x2b
|
||||
db 0x6b, 0xe8, 0x6d, 0x1f, 0xde, 0x56, 0xb5, 0x30, 0x2c, 0x76, 0xae, 0x30, 0xf3, 0x9a, 0xd2, 0x67
|
||||
db 0x09, 0xad, 0xe8, 0x3d, 0x53, 0xb9, 0x15, 0xb6, 0x90, 0xb8, 0x04, 0x74, 0xa3, 0x72, 0x64, 0xb7
|
||||
db 0xad, 0x10, 0xf1, 0x72, 0x4c, 0x6b, 0x42, 0x24, 0x67, 0xa5, 0x15, 0xd4, 0xf2, 0x89, 0x67, 0x8a
|
||||
db 0x12, 0x66, 0x23, 0x78, 0x81, 0xf8, 0x96, 0x89, 0xa9, 0xa2, 0x3c, 0x3d, 0x82, 0x6b, 0xa2, 0x19
|
||||
db 0xb0, 0x12, 0x97, 0x68, 0xab, 0x58, 0xf6, 0x00, 0x72, 0x19, 0xd2, 0x1e, 0x03, 0x9d, 0x7d, 0xc9
|
||||
db 0xc8, 0x55, 0xdf, 0x98, 0x22, 0x43, 0x86, 0x1c, 0xcc, 0xe9, 0x1b, 0x89, 0xda, 0xfe, 0x9b, 0xb2
|
||||
db 0x47, 0x21, 0x0f, 0x71, 0x28, 0xbd, 0xb0, 0x88, 0x38, 0xac, 0xb5, 0x7f, 0x88, 0x5e, 0xe9, 0xc4
|
||||
db 0xe4, 0x5b, 0x3e, 0xd0, 0x2a, 0x8c, 0xdf, 0xa7, 0xea, 0x95, 0xd3, 0xc2, 0xee, 0xd1, 0x70, 0x6c
|
||||
db 0x18, 0x77, 0xc1, 0x38, 0x7b, 0xfc, 0xa9, 0x58, 0x92, 0xe8, 0xc6, 0xcd, 0x07, 0x5d, 0x3d, 0x76
|
||||
db 0xf4, 0x4c, 0x5b, 0x25, 0x7f, 0x9b, 0x02, 0x41, 0x78, 0x39, 0x9e, 0x3e, 0x4c, 0xa2, 0x79, 0xca
|
||||
db 0x1c, 0xe9, 0xf2, 0x9a, 0xaf, 0x6d, 0xfa, 0x57, 0x10, 0xc7, 0xfd, 0x5f, 0x20, 0x80, 0xf5, 0x65
|
||||
db 0x3c, 0x77, 0xfb, 0xa8, 0xdf, 0x94, 0x16, 0x4f, 0xc0, 0x78, 0x00, 0x76, 0x03, 0x8c, 0x82, 0x10
|
||||
db 0x7f, 0x07, 0xe0, 0x02, 0x92, 0xbb, 0xf9, 0x2e, 0xfa, 0x3d, 0x88, 0xc8, 0x24, 0x27, 0xa6, 0x1e
|
||||
db 0x04, 0x90, 0xf6, 0xf8, 0x76, 0x0a, 0x4c, 0x94, 0xbc, 0xb7, 0x8d, 0x8b, 0xf9, 0x65, 0xf5, 0x07
|
||||
db 0x7f, 0xc1, 0x37, 0x78, 0xa1, 0x1f, 0xc4, 0x10, 0x6c, 0x29, 0x5e, 0x7e, 0x32, 0x24, 0x92, 0x09
|
||||
@@ -0,0 +1,59 @@
|
||||
%ifdef CONFIG
|
||||
{
|
||||
"HostFeatures": ["AVX"],
|
||||
"RegData": {
|
||||
"XMM0": ["0x4142434445467778", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM1": ["0x4142434477784748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM2": ["0x4142777845464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM3": ["0x7778434445464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM4": ["0x4142434445464748", "0x5152535455567778", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM5": ["0x4142434445464748", "0x5152535477785758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM6": ["0x4142434445464748", "0x5152777855565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM7": ["0x4142434445464748", "0x7778535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM8": ["0x4142434445467778", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM9": ["0x4142434477784748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM10": ["0x4142777845464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM11": ["0x7778434445464748", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM12": ["0x4142434445464748", "0x5152535455567778", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM13": ["0x4142434445464748", "0x5152535477785758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM14": ["0x4142434445464748", "0x5152777855565758", "0x0000000000000000", "0x0000000000000000"],
|
||||
"XMM15": ["0x4142434445464748", "0x7778535455565758", "0x0000000000000000", "0x0000000000000000"]
|
||||
}
|
||||
}
|
||||
%endif
|
||||
|
||||
lea rdx, [rel .data]
|
||||
|
||||
mov rax, 0x7172737475767778
|
||||
|
||||
vmovapd ymm0, [rdx]
|
||||
|
||||
vpinsrw xmm1, xmm0, eax, 1
|
||||
vpinsrw xmm2, xmm0, eax, 2
|
||||
vpinsrw xmm3, xmm0, eax, 3
|
||||
vpinsrw xmm4, xmm0, eax, 4
|
||||
vpinsrw xmm5, xmm0, eax, 5
|
||||
vpinsrw xmm6, xmm0, eax, 6
|
||||
vpinsrw xmm7, xmm0, eax, 7
|
||||
|
||||
vpinsrw xmm8, xmm0, [rdx + 32], 0
|
||||
vpinsrw xmm9, xmm0, [rdx + 32], 1
|
||||
vpinsrw xmm10, xmm0, [rdx + 32], 2
|
||||
vpinsrw xmm11, xmm0, [rdx + 32], 3
|
||||
vpinsrw xmm12, xmm0, [rdx + 32], 4
|
||||
vpinsrw xmm13, xmm0, [rdx + 32], 5
|
||||
vpinsrw xmm14, xmm0, [rdx + 32], 6
|
||||
vpinsrw xmm15, xmm0, [rdx + 32], 7
|
||||
|
||||
vpinsrw xmm0, xmm0, eax, 0
|
||||
|
||||
hlt
|
||||
|
||||
align 32
|
||||
.data:
|
||||
dq 0x4142434445464748
|
||||
dq 0x5152535455565758
|
||||
dq 0x6162636465666768
|
||||
dq 0x7172737475767778
|
||||
|
||||
dq 0x7172737475767778
|
||||
Reference in new issue
Block a user