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Merge pull request #3955 from alyssarosenzweig/opt/pop-final

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Rearrange SRA to let us coalesce cmpxchg moves
This commit is contained in:
Ryan Houdek authored and GitHub committed 2024-08-20 17:36:11 -07:00
2 parents 2a170cfdec a299d6b1a5
commit 877b2f4fef
43 files changed
+30090 -30101
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FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
+4 -3
View File
@@ -29,11 +29,12 @@ namespace FEXCore::CPU {
namespace x64 {
#ifndef _M_ARM_64EC
// All but x19 and x29 are caller saved
// Note that rax/rdx are rearranged here so we can coalesce cmpxchg.
constexpr std::array<ARMEmitter::Register, 18> SRA = {
ARMEmitter::Reg::r4,
ARMEmitter::Reg::r7,
ARMEmitter::Reg::r5,
ARMEmitter::Reg::r6,
ARMEmitter::Reg::r7,
ARMEmitter::Reg::r8,
ARMEmitter::Reg::r9,
ARMEmitter::Reg::r10,
@@ -194,12 +195,12 @@ namespace x64 {
} // namespace x64
namespace x32 {
// All but x19 and x29 are caller saved
// All but x19 and x29 are caller saved. eax/edx rearranged for cmpxchg.
constexpr std::array<ARMEmitter::Register, 10> SRA = {
ARMEmitter::Reg::r4,
ARMEmitter::Reg::r7,
ARMEmitter::Reg::r5,
ARMEmitter::Reg::r6,
ARMEmitter::Reg::r7,
ARMEmitter::Reg::r8,
ARMEmitter::Reg::r9,
ARMEmitter::Reg::r10,
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+22 -22
View File
@@ -621,7 +621,7 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"bic w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x4, x26"
]
@@ -632,7 +632,7 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"bic x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x4, x26"
]
@@ -644,10 +644,10 @@
],
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"lsl w20, w20, w5",
"bic w20, w7, w20",
"tst x5, #0xe0",
"csel w4, w7, w20, ne",
"lsl w20, w20, w7",
"bic w20, w6, w20",
"tst x7, #0xe0",
"csel w4, w6, w20, ne",
"cset w20, eq",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -660,10 +660,10 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"lsl x20, x20, x5",
"bic x20, x7, x20",
"tst x5, #0xc0",
"csel x4, x7, x20, ne",
"lsl x20, x20, x7",
"bic x20, x6, x20",
"tst x7, #0xc0",
"csel x4, x6, x20, ne",
"cset w20, eq",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -675,10 +675,10 @@
"Map 2 0b11 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x0, x6",
"mov x1, x7",
"mov w4, #0x0",
"cbz w5, #+0x2c",
"cbz w7, #+0x2c",
"neg w2, w1",
"and w2, w2, w1",
"sbfx w3, w0, #0, #1",
@@ -697,10 +697,10 @@
"Map 2 0b11 0xf5 64-bit"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x0, x6",
"mov x1, x7",
"mov x4, #0x0",
"cbz x5, #+0x2c",
"cbz x7, #+0x2c",
"neg x2, x1",
"and x2, x2, x1",
"sbfx x3, x0, #0, #1",
@@ -719,12 +719,12 @@
"Map 2 0b00 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"uxtb w20, w5",
"lsr w21, w7, w20",
"uxtb w20, w7",
"lsr w21, w6, w20",
"mov w22, #0x0",
"cmp w20, #0x1f (31)",
"csel w20, w21, w22, ls",
"ubfx w21, w5, #8, #8",
"ubfx w21, w7, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl w22, w22, w21",
"bic w22, w20, w22",
@@ -739,12 +739,12 @@
"Map 2 0b00 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"uxtb x20, w5",
"lsr x21, x7, x20",
"uxtb x20, w7",
"lsr x21, x6, x20",
"mov w22, #0x0",
"cmp x20, #0x3f (63)",
"csel x20, x21, x22, ls",
"ubfx x21, x5, #8, #8",
"ubfx x21, x7, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl x22, x22, x21",
"bic x22, x20, x22",
unittests/InstructionCountCI/Atomics.json
+79 -79
View File
@@ -15,11 +15,11 @@
"ExpectedInstructionCount": 8,
"Comment": "0x00",
"ExpectedArm64ASM": [
"ldaddalb w5, w20, [x4]",
"eor w27, w20, w5",
"ldaddalb w7, w20, [x4]",
"eor w27, w20, w7",
"lsl w0, w20, #24",
"cmn w0, w5, lsl #24",
"add w26, w20, w5",
"cmn w0, w7, lsl #24",
"add w26, w20, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -29,11 +29,11 @@
"ExpectedInstructionCount": 8,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddalh w5, w20, [x4]",
"eor w27, w20, w5",
"ldaddalh w7, w20, [x4]",
"eor w27, w20, w7",
"lsl w0, w20, #16",
"cmn w0, w5, lsl #16",
"add w26, w20, w5",
"cmn w0, w7, lsl #16",
"add w26, w20, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -43,9 +43,9 @@
"ExpectedInstructionCount": 6,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal w5, w20, [x4]",
"eor w27, w20, w5",
"adds w26, w20, w5",
"ldaddal w7, w20, [x4]",
"eor w27, w20, w7",
"adds w26, w20, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -55,8 +55,8 @@
"ExpectedInstructionCount": 6,
"Comment": "0x08",
"ExpectedArm64ASM": [
"ldsetalb w5, w20, [x4]",
"orr w26, w20, w5",
"ldsetalb w7, w20, [x4]",
"orr w26, w20, w7",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -67,8 +67,8 @@
"ExpectedInstructionCount": 6,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetalh w5, w20, [x4]",
"orr w26, w20, w5",
"ldsetalh w7, w20, [x4]",
"orr w26, w20, w7",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -79,8 +79,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w5, w20, [x4]",
"orr w26, w20, w5",
"ldsetal w7, w20, [x4]",
"orr w26, w20, w7",
"cmp w26, #0x0 (0)"
]
},
@@ -88,10 +88,10 @@
"ExpectedInstructionCount": 18,
"Comment": "0x10",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, w5",
"uxtb w21, w5",
"eor w27, w20, w7",
"uxtb w21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxtb w26, w23",
@@ -112,10 +112,10 @@
"ExpectedInstructionCount": 18,
"Comment": "0x11",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"ldaddalh w20, w20, [x4]",
"eor w27, w20, w5",
"uxth w21, w5",
"eor w27, w20, w7",
"uxth w21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxth w26, w23",
@@ -136,13 +136,13 @@
"ExpectedInstructionCount": 10,
"Comment": "0x11",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"ldaddal w20, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"adcs w26, w20, w5",
"adcs w26, w20, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -152,12 +152,12 @@
"ExpectedInstructionCount": 20,
"Comment": "0x18",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"uxtb w20, w20",
"uxtb w21, w5",
"uxtb w21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -178,12 +178,12 @@
"ExpectedInstructionCount": 20,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"uxth w20, w20",
"uxth w21, w5",
"uxth w21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -204,20 +204,20 @@
"ExpectedInstructionCount": 5,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"sbcs w26, w20, w5"
"eor w27, w20, w7",
"sbcs w26, w20, w7"
]
},
"lock and byte [rax], cl": {
"ExpectedInstructionCount": 7,
"Comment": "0x20",
"ExpectedArm64ASM": [
"mvn w1, w5",
"mvn w1, w7",
"ldclralb w1, w20, [x4]",
"and w26, w20, w5",
"and w26, w20, w7",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -228,9 +228,9 @@
"ExpectedInstructionCount": 7,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"mvn w1, w7",
"ldclralh w1, w20, [x4]",
"and w26, w20, w5",
"and w26, w20, w7",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -241,9 +241,9 @@
"ExpectedInstructionCount": 6,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"mvn w1, w7",
"ldclral w1, w20, [x4]",
"ands w26, w20, w5",
"ands w26, w20, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -253,42 +253,42 @@
"ExpectedInstructionCount": 6,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w5",
"neg w1, w7",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"lsl w0, w20, #24",
"cmp w0, w5, lsl #24",
"sub w26, w20, w5"
"cmp w0, w7, lsl #24",
"sub w26, w20, w7"
]
},
"lock sub word [rax], cx": {
"ExpectedInstructionCount": 6,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w5",
"neg w1, w7",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"lsl w0, w20, #16",
"cmp w0, w5, lsl #16",
"sub w26, w20, w5"
"cmp w0, w7, lsl #16",
"sub w26, w20, w7"
]
},
"lock sub dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x29",
"ExpectedArm64ASM": [
"neg w1, w5",
"neg w1, w7",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"subs w26, w20, w5"
"eor w27, w20, w7",
"subs w26, w20, w7"
]
},
"lock xor byte [rax], cl": {
"ExpectedInstructionCount": 6,
"Comment": "0x30",
"ExpectedArm64ASM": [
"ldeoralb w5, w20, [x4]",
"eor w26, w20, w5",
"ldeoralb w7, w20, [x4]",
"eor w26, w20, w7",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -299,8 +299,8 @@
"ExpectedInstructionCount": 6,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoralh w5, w20, [x4]",
"eor w26, w20, w5",
"ldeoralh w7, w20, [x4]",
"eor w26, w20, w7",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -311,8 +311,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w5, w20, [x4]",
"eor w26, w20, w5",
"ldeoral w7, w20, [x4]",
"eor w26, w20, w7",
"cmp w26, #0x0 (0)"
]
},
@@ -320,9 +320,9 @@
"ExpectedInstructionCount": 6,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal x5, x20, [x4]",
"eor w27, w20, w5",
"adds x26, x20, x5",
"ldaddal x7, x20, [x4]",
"eor w27, w20, w7",
"adds x26, x20, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -332,43 +332,43 @@
"ExpectedInstructionCount": 2,
"Comment": "0x86",
"ExpectedArm64ASM": [
"swpalb w5, w20, [x4]",
"bfxil x5, x20, #0, #8"
"swpalb w7, w20, [x4]",
"bfxil x7, x20, #0, #8"
]
},
"xchg word [rax], cx": {
"ExpectedInstructionCount": 2,
"Comment": "0x87",
"ExpectedArm64ASM": [
"swpalh w5, w20, [x4]",
"bfxil x5, x20, #0, #16"
"swpalh w7, w20, [x4]",
"bfxil x7, x20, #0, #16"
]
},
"xchg dword [rax], ecx": {
"ExpectedInstructionCount": 1,
"Comment": "0x87",
"ExpectedArm64ASM": [
"swpal w5, w5, [x4]"
"swpal w7, w7, [x4]"
]
},
"xchg qword [rax], rcx": {
"ExpectedInstructionCount": 1,
"Comment": "0x87",
"ExpectedArm64ASM": [
"swpal x5, x5, [x4]"
"swpal x7, x7, [x4]"
]
},
"xadd byte [rax], bl": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w20, w6",
"ldaddalb w20, w21, [x4]",
"eor w27, w21, w20",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, w20",
"bfxil x7, x21, #0, #8",
"bfxil x6, x21, #0, #8",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -378,13 +378,13 @@
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"ldaddalh w20, w21, [x4]",
"eor w27, w21, w20",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20",
"bfxil x7, x21, #0, #16",
"bfxil x6, x21, #0, #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -394,10 +394,10 @@
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"eor w27, w7, w20",
"adds w26, w7, w20",
"mov w20, w6",
"ldaddal w20, w6, [x4]",
"eor w27, w6, w20",
"adds w26, w6, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -407,13 +407,13 @@
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"ldaddal x7, x20, [x4]",
"eor w27, w20, w7",
"adds x26, x20, x7",
"ldaddal x6, x20, [x4]",
"eor w27, w20, w6",
"adds x26, x20, x6",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x7, x20"
"mov x6, x20"
]
},
"lock add byte [rax], 1": {
unittests/InstructionCountCI/Crypto/H0F38.json
+5 -5
View File
@@ -95,7 +95,7 @@
"0xf2 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"crc32cb w4, w4, w7"
"crc32cb w4, w4, w6"
]
},
"crc32 eax, bx": {
@@ -104,7 +104,7 @@
"0xf2 0x0f 0x38 0xf1"
],
"ExpectedArm64ASM": [
"crc32ch w4, w4, w7"
"crc32ch w4, w4, w6"
]
},
"crc32 eax, ebx": {
@@ -113,7 +113,7 @@
"0xf2 0x0f 0x38 0xf1"
],
"ExpectedArm64ASM": [
"crc32cw w4, w4, w7"
"crc32cw w4, w4, w6"
]
},
"crc32 rax, bl": {
@@ -122,7 +122,7 @@
"0xf2 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"crc32cb w4, w4, w7"
"crc32cb w4, w4, w6"
]
},
"crc32 rax, rbx": {
@@ -131,7 +131,7 @@
"0xf2 0x0f 0x38 0xf1"
],
"ExpectedArm64ASM": [
"crc32cx w4, w4, x7"
"crc32cx w4, w4, x6"
]
}
}
unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+154 -154
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+46 -46
View File
@@ -17,141 +17,141 @@
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldrb w4, [x5, x20, sxtx]"
"ldrb w4, [x7, x20, sxtx]"
]
},
"movzx eax, byte [ecx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldurb w4, [x5, #-256]"
"ldurb w4, [x7, #-256]"
]
},
"movzx eax, byte [ecx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w4, [x5, #255]"
"ldrb w4, [x7, #255]"
]
},
"movzx eax, byte [ecx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w4, [x5, #256]"
"ldrb w4, [x7, #256]"
]
},
"movzx eax, byte [ecx + 4095]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrb w4, [x5, #4095]"
"ldrb w4, [x7, #4095]"
]
},
"movzx eax, byte [ecx + 4096]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x1000",
"ldrb w4, [x5, x20, sxtx]"
"ldrb w4, [x7, x20, sxtx]"
]
},
"movzx eax, word [ecx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldrh w4, [x5, x20, sxtx]"
"ldrh w4, [x7, x20, sxtx]"
]
},
"movzx eax, word [ecx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldurh w4, [x5, #-256]"
"ldurh w4, [x7, #-256]"
]
},
"movzx eax, word [ecx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldurh w4, [x5, #255]"
"ldurh w4, [x7, #255]"
]
},
"movzx eax, word [ecx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrh w4, [x5, #256]"
"ldrh w4, [x7, #256]"
]
},
"movzx eax, word [ecx + 8190]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldrh w4, [x5, #8190]"
"ldrh w4, [x7, #8190]"
]
},
"movzx eax, word [ecx + 8191]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x1fff",
"ldrh w4, [x5, x20, sxtx]"
"ldrh w4, [x7, x20, sxtx]"
]
},
"movzx eax, word [ecx + 8192]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x2000",
"ldrh w4, [x5, x20, sxtx]"
"ldrh w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [ecx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr w4, [x5, x20, sxtx]"
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [ecx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur w4, [x5, #-256]"
"ldur w4, [x7, #-256]"
]
},
"mov eax, dword [ecx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur w4, [x5, #255]"
"ldur w4, [x7, #255]"
]
},
"mov eax, dword [ecx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr w4, [x5, #256]"
"ldr w4, [x7, #256]"
]
},
"mov eax, dword [ecx + 16380]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr w4, [x5, #16380]"
"ldr w4, [x7, #16380]"
]
},
"mov eax, dword [ecx + 16381]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffd",
"ldr w4, [x5, x20, sxtx]"
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [ecx + 16382]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffe",
"ldr w4, [x5, x20, sxtx]"
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [ecx + 16383]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3fff",
"ldr w4, [x5, x20, sxtx]"
"ldr w4, [x7, x20, sxtx]"
]
},
"mov eax, dword [ecx + 16384]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"add w20, w5, #0x4000 (16384)",
"add w20, w7, #0x4000 (16384)",
"ldr w4, [x20]"
]
},
@@ -159,52 +159,52 @@
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffb",
"ldr s16, [x5, x20, sxtx]"
"ldr s16, [x7, x20, sxtx]"
]
},
"movss xmm0, [ecx + 16380]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr s16, [x5, #16380]"
"ldr s16, [x7, #16380]"
]
},
"movss xmm0, [ecx + 16381]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov w20, #0x3ffd",
"ldr s16, [x5, x20, sxtx]"
"ldr s16, [x7, x20, sxtx]"
]
},
"movss xmm0, [ecx - 257]": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr s16, [x5, x20, sxtx]"
"ldr s16, [x7, x20, sxtx]"
]
},
"movss xmm0, [ecx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur s16, [x5, #-256]"
"ldur s16, [x7, #-256]"
]
},
"movss xmm0, [ecx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur s16, [x5, #255]"
"ldur s16, [x7, #255]"
]
},
"movss xmm0, [ecx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr s16, [x5, #256]"
"ldr s16, [x7, #256]"
]
},
"movsd xmm0, [ecx + 32759]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0x7ff7",
"add w20, w5, w20",
"add w20, w7, w20",
"ldr d16, [x20]"
]
},
@@ -212,7 +212,7 @@
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0x7ff8",
"add w20, w5, w20",
"add w20, w7, w20",
"ldr d16, [x20]"
]
},
@@ -220,7 +220,7 @@
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0x7ff9",
"add w20, w5, w20",
"add w20, w7, w20",
"ldr d16, [x20]"
]
},
@@ -228,32 +228,32 @@
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr d16, [x5, x20, sxtx]"
"ldr d16, [x7, x20, sxtx]"
]
},
"movsd xmm0, [ecx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x5, #-256]"
"ldur d16, [x7, #-256]"
]
},
"movsd xmm0, [ecx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x5, #255]"
"ldur d16, [x7, #255]"
]
},
"movsd xmm0, [ecx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr d16, [x5, #256]"
"ldr d16, [x7, #256]"
]
},
"movq xmm0, [ecx + 65519]": {
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0xffef",
"add w20, w5, w20",
"add w20, w7, w20",
"ldr d16, [x20]"
]
},
@@ -261,7 +261,7 @@
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0xfff0",
"add w20, w5, w20",
"add w20, w7, w20",
"ldr d16, [x20]"
]
},
@@ -269,7 +269,7 @@
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"mov w20, #0xfff1",
"add w20, w5, w20",
"add w20, w7, w20",
"ldr d16, [x20]"
]
},
@@ -277,39 +277,39 @@
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"mov x20, #0xfffffffffffffeff",
"ldr d16, [x5, x20, sxtx]"
"ldr d16, [x7, x20, sxtx]"
]
},
"movq xmm0, [ecx - 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x5, #-256]"
"ldur d16, [x7, #-256]"
]
},
"movq xmm0, [ecx + 255]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldur d16, [x5, #255]"
"ldur d16, [x7, #255]"
]
},
"movq xmm0, [ecx + 256]": {
"ExpectedInstructionCount": 1,
"ExpectedArm64ASM": [
"ldr d16, [x5, #256]"
"ldr d16, [x7, #256]"
]
},
"mov ebx, fs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr w20, [x28, #968]",
"ldr w7, [x20, #20]"
"ldr w6, [x20, #20]"
]
},
"mov ebx, gs:0x14": {
"ExpectedInstructionCount": 2,
"ExpectedArm64ASM": [
"ldr w20, [x28, #960]",
"ldr w7, [x20, #20]"
"ldr w6, [x20, #20]"
]
},
"Multiple segment registers": {
@@ -322,7 +322,7 @@
"ldr w20, [x28, #960]",
"ldr w4, [x20, #256]",
"ldr w20, [x28, #960]",
"ldr w7, [x20, #20]"
"ldr w6, [x20, #20]"
]
}
}
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+87 -87
View File
@@ -27,7 +27,7 @@
],
"ExpectedArm64ASM": [
"strh w4, [x8, #-2]!",
"strh w7, [x8, #-2]!"
"strh w6, [x8, #-2]!"
]
},
"push rax, rbx": {
@@ -41,7 +41,7 @@
],
"ExpectedArm64ASM": [
"str x4, [x8, #-8]!",
"str x7, [x8, #-8]!"
"str x6, [x8, #-8]!"
]
},
"adds xmm0, xmm1, xmm2": {
@@ -225,7 +225,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x78",
@@ -260,13 +260,13 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"add x23, x0, x2",
"add x22, x1, x2",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x5, x20"
"mov x7, x20"
]
},
"positive rep movsw": {
@@ -282,7 +282,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x78",
@@ -317,13 +317,13 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"add x23, x0, x2, lsl #1",
"add x22, x1, x2, lsl #1",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x5, x20"
"mov x7, x20"
]
},
"positive rep movsd": {
@@ -339,7 +339,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x78",
@@ -374,13 +374,13 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"add x23, x0, x2, lsl #2",
"add x22, x1, x2, lsl #2",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x5, x20"
"mov x7, x20"
]
},
"positive rep movsq": {
@@ -396,7 +396,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x78",
@@ -431,13 +431,13 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"add x23, x0, x2, lsl #3",
"add x22, x1, x2, lsl #3",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x5, x20"
"mov x7, x20"
]
},
"negative rep movsb": {
@@ -452,7 +452,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x88",
@@ -491,10 +491,10 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"sub x22, x0, x2",
"sub x21, x1, x2",
"mov w5, #0x0",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
@@ -512,7 +512,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x88",
@@ -551,10 +551,10 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"sub x22, x0, x2, lsl #1",
"sub x21, x1, x2, lsl #1",
"mov w5, #0x0",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
@@ -572,7 +572,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x88",
@@ -611,10 +611,10 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"sub x22, x0, x2, lsl #2",
"sub x21, x1, x2, lsl #2",
"mov w5, #0x0",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
@@ -632,7 +632,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
"cbz x0, #+0x88",
@@ -671,10 +671,10 @@
"cbnz x0, #-0xc",
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"mov x2, x7",
"sub x22, x0, x2, lsl #3",
"sub x21, x1, x2, lsl #3",
"mov w5, #0x0",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
@@ -694,7 +694,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"uxtb w22, w4",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x20 (32)",
@@ -718,9 +718,9 @@
"strb w22, [x1], #1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5",
"add x11, x11, x7",
"strb w21, [x28, #986]",
"mov x5, x20"
"mov x7, x20"
]
},
"positive rep stosw": {
@@ -737,7 +737,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"uxth w22, w4",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x10 (16)",
@@ -761,9 +761,9 @@
"strh w22, [x1], #2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #1",
"add x11, x11, x7, lsl #1",
"strb w21, [x28, #986]",
"mov x5, x20"
"mov x7, x20"
]
},
"positive rep stosd": {
@@ -780,7 +780,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"mov w22, w4",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x8 (8)",
@@ -804,9 +804,9 @@
"str w22, [x1], #4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #2",
"add x11, x11, x7, lsl #2",
"strb w21, [x28, #986]",
"mov x5, x20"
"mov x7, x20"
]
},
"positive rep stosq": {
@@ -822,7 +822,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x4 (4)",
@@ -846,9 +846,9 @@
"str x4, [x1], #8",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #3",
"add x11, x11, x7, lsl #3",
"strb w21, [x28, #986]",
"mov x5, x20"
"mov x7, x20"
]
},
"negative rep stosb": {
@@ -864,7 +864,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"uxtb w21, w4",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1f (31)",
@@ -890,8 +890,8 @@
"strb w21, [x1], #-1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5",
"mov w5, #0x0",
"sub x11, x11, x7",
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
@@ -908,7 +908,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"uxth w21, w4",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1e (30)",
@@ -934,8 +934,8 @@
"strh w21, [x1], #-2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #1",
"mov w5, #0x0",
"sub x11, x11, x7, lsl #1",
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
@@ -952,7 +952,7 @@
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov w21, w4",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1c (28)",
@@ -978,8 +978,8 @@
"str w21, [x1], #-4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #2",
"mov w5, #0x0",
"sub x11, x11, x7, lsl #2",
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
@@ -995,7 +995,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov x0, x5",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x18 (24)",
@@ -1021,8 +1021,8 @@
"str x4, [x1], #-8",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #3",
"mov w5, #0x0",
"sub x11, x11, x7, lsl #3",
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
@@ -1154,8 +1154,8 @@
"pop rbx"
],
"ExpectedArm64ASM": [
"str x5, [x8, #8]",
"str x7, [x8, #-8]!",
"str x7, [x8, #8]",
"str x6, [x8, #-8]!",
"str x9, [x8, #-8]!",
"str x10, [x8, #-8]!",
"str x11, [x8, #-8]!",
@@ -1164,19 +1164,19 @@
"str x19, [x8, #-8]!",
"str x29, [x8, #-8]!",
"sub x8, x8, #0x18 (24)",
"ldr w5, [x6, #36]",
"ldr w10, [x6]",
"ldr w9, [x6, #4]",
"ldr w19, [x6, #8]",
"ldr w29, [x6, #12]",
"ldr w16, [x6, #16]",
"ldr w17, [x6, #20]",
"ldr w15, [x6, #24]",
"ldr w7, [x6, #28]",
"ldr w11, [x6, #32]",
"ldr w7, [x5, #36]",
"ldr w10, [x5]",
"ldr w9, [x5, #4]",
"ldr w19, [x5, #8]",
"ldr w29, [x5, #12]",
"ldr w16, [x5, #16]",
"ldr w17, [x5, #20]",
"ldr w15, [x5, #24]",
"ldr w6, [x5, #28]",
"ldr w11, [x5, #32]",
"mov w20, #0x13",
"mul w4, w5, w20",
"str w5, [x8, #104]",
"mul w4, w7, w20",
"str w7, [x8, #104]",
"mov w21, #0x1000000",
"add w4, w4, w21",
"lsr w4, w4, #25",
@@ -1194,11 +1194,11 @@
"asr w4, w4, #25",
"add w4, w4, w15",
"asr w4, w4, #26",
"add w4, w4, w7",
"add w4, w4, w6",
"asr w4, w4, #25",
"add w4, w4, w11",
"asr w4, w4, #26",
"add w4, w4, w5",
"add w4, w4, w7",
"asr w4, w4, #25",
"mul w4, w4, w20",
"add w10, w10, w4",
@@ -1207,20 +1207,20 @@
"add w9, w9, w4",
"lsl w4, w4, #26",
"sub w10, w10, w4",
"mov w5, w9",
"mov w7, w9",
"ldr x4, [x8, #96]",
"asr w5, w5, #25",
"add w19, w19, w5",
"lsl w5, w5, #25",
"mov w6, w19",
"sub w9, w9, w5",
"asr w6, w6, #26",
"add w29, w29, w6",
"asr w7, w7, #25",
"add w19, w19, w7",
"lsl w7, w7, #25",
"mov w5, w19",
"sub w9, w9, w7",
"asr w5, w5, #26",
"add w29, w29, w5",
"str w10, [x4]",
"mov w12, w29",
"lsl w6, w6, #26",
"lsl w5, w5, #26",
"asr w12, w12, #25",
"sub w19, w19, w6",
"sub w19, w19, w5",
"add w16, w16, w12",
"str w9, [x4, #4]",
"mov w13, w16",
@@ -1238,36 +1238,36 @@
"str w15, [x8, #112]",
"mov x10, x4",
"asr w15, w15, #26",
"add w7, w7, w15",
"add w6, w6, w15",
"str w16, [x4, #16]",
"str w7, [x8, #120]",
"asr w7, w7, #25",
"add w11, w11, w7",
"str w6, [x8, #120]",
"asr w6, w6, #25",
"add w11, w11, w6",
"str w11, [x8]",
"asr w11, w11, #26",
"ldr w20, [x8, #104]",
"add w20, w20, w11",
"str w20, [x8, #104]",
"lsl w14, w14, #25",
"ldr w5, [x8, #104]",
"ldr w7, [x8, #104]",
"sub w17, w17, w14",
"str w17, [x4, #20]",
"ldr w4, [x8, #112]",
"lsl w15, w15, #26",
"sub w4, w4, w15",
"lsl w7, w7, #25",
"lsl w6, w6, #25",
"str w4, [x10, #24]",
"ldr w4, [x8, #120]",
"sub w4, w4, w7",
"sub w4, w4, w6",
"lsl w11, w11, #26",
"str w4, [x10, #28]",
"ldr w4, [x8]",
"sub w4, w4, w11",
"str w4, [x10, #32]",
"mov w4, w5",
"mov w4, w7",
"and w4, w4, #0xfe000000",
"sub w5, w5, w4",
"str w5, [x10, #36]",
"sub w7, w7, w4",
"str w7, [x10, #36]",
"mvn w27, w8",
"adds x26, x8, #0x18 (24)",
"mov x8, x26",
@@ -1278,7 +1278,7 @@
"ldr x11, [x8], #8",
"ldr x10, [x8], #8",
"ldr x9, [x8], #8",
"ldr x7, [x8], #8",
"ldr x6, [x8], #8",
"cfinv"
]
}
unittests/InstructionCountCI/FlagM/Atomics.json
+73 -73
View File
@@ -16,11 +16,11 @@
"ExpectedInstructionCount": 6,
"Comment": "0x00",
"ExpectedArm64ASM": [
"ldaddalb w5, w20, [x4]",
"eor w27, w20, w5",
"ldaddalb w7, w20, [x4]",
"eor w27, w20, w7",
"lsl w0, w20, #24",
"cmn w0, w5, lsl #24",
"add w26, w20, w5",
"cmn w0, w7, lsl #24",
"add w26, w20, w7",
"cfinv"
]
},
@@ -28,11 +28,11 @@
"ExpectedInstructionCount": 6,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddalh w5, w20, [x4]",
"eor w27, w20, w5",
"ldaddalh w7, w20, [x4]",
"eor w27, w20, w7",
"lsl w0, w20, #16",
"cmn w0, w5, lsl #16",
"add w26, w20, w5",
"cmn w0, w7, lsl #16",
"add w26, w20, w7",
"cfinv"
]
},
@@ -40,9 +40,9 @@
"ExpectedInstructionCount": 4,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal w5, w20, [x4]",
"eor w27, w20, w5",
"adds w26, w20, w5",
"ldaddal w7, w20, [x4]",
"eor w27, w20, w7",
"adds w26, w20, w7",
"cfinv"
]
},
@@ -50,8 +50,8 @@
"ExpectedInstructionCount": 4,
"Comment": "0x08",
"ExpectedArm64ASM": [
"ldsetalb w5, w20, [x4]",
"orr w26, w20, w5",
"ldsetalb w7, w20, [x4]",
"orr w26, w20, w7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -60,8 +60,8 @@
"ExpectedInstructionCount": 4,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetalh w5, w20, [x4]",
"orr w26, w20, w5",
"ldsetalh w7, w20, [x4]",
"orr w26, w20, w7",
"cmn wzr, w26, lsl #16",
"cfinv"
]
@@ -70,8 +70,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w5, w20, [x4]",
"orr w26, w20, w5",
"ldsetal w7, w20, [x4]",
"orr w26, w20, w7",
"cmp w26, #0x0 (0)"
]
},
@@ -79,10 +79,10 @@
"ExpectedInstructionCount": 15,
"Comment": "0x10",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, w5",
"uxtb w21, w5",
"eor w27, w20, w7",
"uxtb w21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxtb w26, w23",
@@ -100,10 +100,10 @@
"ExpectedInstructionCount": 15,
"Comment": "0x11",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"ldaddalh w20, w20, [x4]",
"eor w27, w20, w5",
"uxth w21, w5",
"eor w27, w20, w7",
"uxth w21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxth w26, w23",
@@ -121,11 +121,11 @@
"ExpectedInstructionCount": 6,
"Comment": "0x11",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"ldaddal w20, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"cfinv",
"adcs w26, w20, w5",
"adcs w26, w20, w7",
"cfinv"
]
},
@@ -133,12 +133,12 @@
"ExpectedInstructionCount": 17,
"Comment": "0x18",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"uxtb w20, w20",
"uxtb w21, w5",
"uxtb w21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -156,12 +156,12 @@
"ExpectedInstructionCount": 17,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"uxth w20, w20",
"uxth w21, w5",
"uxth w21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -179,20 +179,20 @@
"ExpectedInstructionCount": 5,
"Comment": "0x19",
"ExpectedArm64ASM": [
"cinc w20, w5, lo",
"cinc w20, w7, lo",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"sbcs w26, w20, w5"
"eor w27, w20, w7",
"sbcs w26, w20, w7"
]
},
"lock and byte [rax], cl": {
"ExpectedInstructionCount": 5,
"Comment": "0x20",
"ExpectedArm64ASM": [
"mvn w1, w5",
"mvn w1, w7",
"ldclralb w1, w20, [x4]",
"and w26, w20, w5",
"and w26, w20, w7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -201,9 +201,9 @@
"ExpectedInstructionCount": 5,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"mvn w1, w7",
"ldclralh w1, w20, [x4]",
"and w26, w20, w5",
"and w26, w20, w7",
"cmn wzr, w26, lsl #16",
"cfinv"
]
@@ -212,9 +212,9 @@
"ExpectedInstructionCount": 4,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"mvn w1, w7",
"ldclral w1, w20, [x4]",
"ands w26, w20, w5",
"ands w26, w20, w7",
"cfinv"
]
},
@@ -222,42 +222,42 @@
"ExpectedInstructionCount": 6,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w5",
"neg w1, w7",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"lsl w0, w20, #24",
"cmp w0, w5, lsl #24",
"sub w26, w20, w5"
"cmp w0, w7, lsl #24",
"sub w26, w20, w7"
]
},
"lock sub word [rax], cx": {
"ExpectedInstructionCount": 6,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w5",
"neg w1, w7",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"eor w27, w20, w7",
"lsl w0, w20, #16",
"cmp w0, w5, lsl #16",
"sub w26, w20, w5"
"cmp w0, w7, lsl #16",
"sub w26, w20, w7"
]
},
"lock sub dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x29",
"ExpectedArm64ASM": [
"neg w1, w5",
"neg w1, w7",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"subs w26, w20, w5"
"eor w27, w20, w7",
"subs w26, w20, w7"
]
},
"lock xor byte [rax], cl": {
"ExpectedInstructionCount": 4,
"Comment": "0x30",
"ExpectedArm64ASM": [
"ldeoralb w5, w20, [x4]",
"eor w26, w20, w5",
"ldeoralb w7, w20, [x4]",
"eor w26, w20, w7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -266,8 +266,8 @@
"ExpectedInstructionCount": 4,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoralh w5, w20, [x4]",
"eor w26, w20, w5",
"ldeoralh w7, w20, [x4]",
"eor w26, w20, w7",
"cmn wzr, w26, lsl #16",
"cfinv"
]
@@ -276,8 +276,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w5, w20, [x4]",
"eor w26, w20, w5",
"ldeoral w7, w20, [x4]",
"eor w26, w20, w7",
"cmp w26, #0x0 (0)"
]
},
@@ -285,9 +285,9 @@
"ExpectedInstructionCount": 4,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal x5, x20, [x4]",
"eor w27, w20, w5",
"adds x26, x20, x5",
"ldaddal x7, x20, [x4]",
"eor w27, w20, w7",
"adds x26, x20, x7",
"cfinv"
]
},
@@ -295,13 +295,13 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w20, w6",
"ldaddalb w20, w21, [x4]",
"eor w27, w21, w20",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, w20",
"bfxil x7, x21, #0, #8",
"bfxil x6, x21, #0, #8",
"cfinv"
]
},
@@ -309,13 +309,13 @@
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"ldaddalh w20, w21, [x4]",
"eor w27, w21, w20",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20",
"bfxil x7, x21, #0, #16",
"bfxil x6, x21, #0, #16",
"cfinv"
]
},
@@ -323,10 +323,10 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"eor w27, w7, w20",
"adds w26, w7, w20",
"mov w20, w6",
"ldaddal w20, w6, [x4]",
"eor w27, w6, w20",
"adds w26, w6, w20",
"cfinv"
]
},
@@ -334,11 +334,11 @@
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"ldaddal x7, x20, [x4]",
"eor w27, w20, w7",
"adds x26, x20, x7",
"ldaddal x6, x20, [x4]",
"eor w27, w20, w6",
"adds x26, x20, x6",
"cfinv",
"mov x7, x20"
"mov x6, x20"
]
},
"lock add byte [rax], 1": {
unittests/InstructionCountCI/FlagM/FlagOpts.json
+47 -49
View File
@@ -18,11 +18,11 @@
"adc rcx, rcx"
],
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"adds x4, x4, x6",
"mov w27, #0x0",
"adcs x26, x5, x5",
"adcs x26, x7, x7",
"cfinv",
"mov x5, x26"
"mov x7, x26"
]
},
"Chained sub": {
@@ -32,10 +32,10 @@
"sbb rcx, rdx"
],
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"eor w27, w5, w6",
"sbcs x26, x5, x6",
"mov x5, x26"
"subs x4, x4, x6",
"eor w27, w7, w5",
"sbcs x26, x7, x5",
"mov x7, x26"
]
},
"Inverted add": {
@@ -46,10 +46,10 @@
"cmc"
],
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"eor w27, w5, w6",
"adcs x26, x5, x6",
"mov x5, x26"
"adds x4, x4, x6",
"eor w27, w7, w5",
"adcs x26, x7, x5",
"mov x7, x26"
]
},
"Inverted sub": {
@@ -60,10 +60,10 @@
"cmc"
],
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"subs x4, x4, x6",
"mov w27, #0x0",
"sbcs x26, x5, x5",
"mov x5, x26",
"sbcs x26, x7, x7",
"mov x7, x26",
"cfinv"
]
},
@@ -75,9 +75,9 @@
"test rcx, rcx"
],
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"adc x5, x5, x5",
"ands x26, x5, x5",
"adds x4, x4, x6",
"adc x7, x7, x7",
"ands x26, x7, x7",
"cfinv"
]
},
@@ -88,7 +88,7 @@
"inc rax"
],
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"adds x4, x4, x6",
"cset w20, lo",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
@@ -104,9 +104,9 @@
"test rax, rdx"
],
"ExpectedArm64ASM": [
"add x4, x4, x7",
"add x4, x4, x6",
"add x4, x4, #0x1 (1)",
"ands x26, x4, x6",
"ands x26, x4, x5",
"cfinv"
]
},
@@ -117,7 +117,7 @@
"dec rax"
],
"ExpectedArm64ASM": [
"subs x4, x4, x7",
"subs x4, x4, x6",
"cset w20, hs",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
@@ -133,9 +133,9 @@
"test rax, rcx"
],
"ExpectedArm64ASM": [
"sub x4, x4, x7",
"sub x4, x4, x6",
"sub x4, x4, #0x1 (1)",
"ands x26, x4, x5",
"ands x26, x4, x7",
"cfinv"
]
},
@@ -185,8 +185,8 @@
"test rax, rdx"
],
"ExpectedArm64ASM": [
"asr x4, x4, x5",
"ands x26, x4, x6",
"asr x4, x4, x7",
"ands x26, x4, x5",
"cfinv"
]
},
@@ -197,14 +197,14 @@
"test rax, rdx"
],
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"cbz x20, #+0x38",
"lsr x20, x4, x5",
"lsr x20, x4, x7",
"cset w21, lo",
"neg x22, x5",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
"sub x23, x5, #0x1 (1)",
"sub x23, x7, #0x1 (1)",
"lsr x23, x4, x23",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
@@ -212,7 +212,7 @@
"orr x4, x20, x21",
"eor x20, x4, x4, lsr #1",
"rmif x20, #62, #nzcV",
"ands x26, x4, x6",
"ands x26, x4, x5",
"cfinv"
]
},
@@ -224,10 +224,10 @@
"test cl, cl"
],
"ExpectedArm64ASM": [
"cmp x4, x7",
"cmp x4, x6",
"cset x20, eq",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -240,10 +240,10 @@
"test cl, cl"
],
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"adds x4, x4, x6",
"cset x20, eq",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -256,10 +256,10 @@
"test cl, cl"
],
"ExpectedArm64ASM": [
"ands w4, w4, w7",
"ands w4, w4, w6",
"cset x20, eq",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -272,36 +272,34 @@
"test cl, cl"
],
"ExpectedArm64ASM": [
"and w26, w4, w7",
"and w26, w4, w6",
"mov x4, x26",
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
"bfxil x5, x20, #0, #8",
"mov x26, x5",
"bfxil x7, x20, #0, #8",
"mov x26, x7",
"cmn wzr, w26, lsl #24",
"cfinv"
]
},
"Dead cmpxchg flags": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"x86Insts": [
"cmpxchg8b [rbp]",
"test rax, rax"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x20, x4",
"mov x21, x6",
"caspal w20, w21, w0, w1, [x9]",
"mov x21, x5",
"caspal w20, w21, w6, w7, [x9]",
"mrs x0, nzcv",
"cmp w20, w4",
"ccmp w21, w6, #nzcv, eq",
"ccmp w21, w5, #nzcv, eq",
"rmif x0, #0, #NzCV",
"csel x4, x20, x4, ne",
"csel x6, x21, x6, ne",
"csel x5, x21, x5, ne",
"ands x26, x4, x4",
"cfinv"
]
unittests/InstructionCountCI/FlagM/H0F38.json
+8 -8
View File
@@ -39,7 +39,7 @@
],
"ExpectedArm64ASM": [
"cset w20, lo",
"mov w21, w7",
"mov w21, w6",
"mov w22, w4",
"add w23, w21, w20",
"add w4, w22, w23",
@@ -62,12 +62,12 @@
],
"ExpectedArm64ASM": [
"cset w20, lo",
"add x21, x7, x20",
"add x21, x6, x20",
"add x4, x4, x21",
"mrs x21, nzcv",
"cmp x4, x7",
"cmp x4, x6",
"cset x22, lo",
"cmp x4, x7",
"cmp x4, x6",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
@@ -83,7 +83,7 @@
],
"ExpectedArm64ASM": [
"cset w20, vs",
"mov w21, w7",
"mov w21, w6",
"mov w22, w4",
"add w23, w21, w20",
"add w4, w22, w23",
@@ -105,12 +105,12 @@
],
"ExpectedArm64ASM": [
"cset w20, vs",
"add x21, x7, x20",
"add x21, x6, x20",
"add x4, x4, x21",
"mrs x21, nzcv",
"cmp x4, x7",
"cmp x4, x6",
"cset x22, lo",
"cmp x4, x7",
"cmp x4, x6",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
unittests/InstructionCountCI/FlagM/HotBlocks.json
+81 -81
View File
@@ -25,15 +25,15 @@
],
"ExpectedArm64ASM": [
"mov w4, #0x1",
"ldaddal x4, x4, [x5]",
"mov x6, x4",
"and w6, w6, #0x1f",
"add x6, x6, #0x1 (1)",
"lsl x6, x6, #6",
"eor w27, w6, w5",
"adds x26, x6, x5",
"ldaddal x4, x4, [x7]",
"mov x5, x4",
"and w5, w5, #0x1f",
"add x5, x5, #0x1 (1)",
"lsl x5, x5, #6",
"eor w27, w5, w7",
"adds x26, x5, x7",
"cfinv",
"mov x6, x26"
"mov x5, x26"
]
},
"FMOD scalar loop": {
@@ -79,61 +79,61 @@
"sub esi, 0x1"
],
"ExpectedArm64ASM": [
"mov w10, w5",
"mov x6, x9",
"mov x4, x7",
"ldr s18, [x6]",
"mov w10, w7",
"mov x5, x9",
"mov x4, x6",
"ldr s18, [x5]",
"add x4, x4, #0x20 (32)",
"fmul s0, s18, s16",
"mov v18.s[0], v0.s[0]",
"add x6, x6, #0x20 (32)",
"add x5, x5, #0x20 (32)",
"ldur s2, [x4, #-32]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-32]",
"ldur s18, [x6, #-28]",
"ldur s18, [x5, #-28]",
"fmul s0, s18, s17",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-28]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-28]",
"ldur s18, [x6, #-24]",
"ldur s18, [x5, #-24]",
"fmul s0, s18, s16",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-24]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-24]",
"ldur s18, [x6, #-20]",
"ldur s18, [x5, #-20]",
"fmul s0, s18, s17",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-20]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-20]",
"ldur s18, [x6, #-16]",
"ldur s18, [x5, #-16]",
"fmul s0, s18, s16",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-16]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-16]",
"ldur s18, [x6, #-12]",
"ldur s18, [x5, #-12]",
"fmul s0, s18, s17",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-12]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-12]",
"ldur s18, [x6, #-8]",
"ldur s18, [x5, #-8]",
"fmul s0, s18, s16",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-8]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-8]",
"ldur s18, [x6, #-4]",
"ldur s18, [x5, #-4]",
"fmul s0, s18, s17",
"mov v18.s[0], v0.s[0]",
"ldur s2, [x4, #-4]",
@@ -183,16 +183,16 @@
"cmp rdi, rax"
],
"ExpectedArm64ASM": [
"mov x6, x4",
"mov x5, x4",
"mov x7, x4",
"mov x19, x10",
"add x4, x4, #0x1 (1)",
"lsr x6, x6, #6",
"and w5, w5, #0x3f",
"lsl x19, x19, x5",
"ldr x20, [x7, x6, sxtx #3]",
"lsr x5, x5, #6",
"and w7, w7, #0x3f",
"lsl x19, x19, x7",
"ldr x20, [x6, x5, sxtx #3]",
"eor x20, x20, x19",
"str x20, [x7, x6, sxtx #3]",
"str x20, [x6, x5, sxtx #3]",
"eor w27, w11, w4",
"subs x26, x11, x4"
]
@@ -233,11 +233,11 @@
"cmp qword [r13+r8*4+0x4],0x0"
],
"ExpectedArm64ASM": [
"ldrh w14, [x6, #4]",
"ldrh w11, [x6, #6]",
"ldrh w14, [x5, #4]",
"ldrh w11, [x5, #6]",
"str w11, [x8, #12]",
"ldrh w7, [x6, #8]",
"ldrh w11, [x6, #10]",
"ldrh w6, [x5, #8]",
"ldrh w11, [x5, #10]",
"str w11, [x8, #16]",
"add x12, x15, x15, lsl #1",
"add x20, x17, x12, lsl #2",
@@ -271,14 +271,14 @@
"str x19, [x8, #-8]!",
"str x17, [x8, #-8]!",
"str x16, [x8, #-8]!",
"str x7, [x8, #-8]!",
"str x6, [x8, #-8]!",
"sub x8, x8, #0x18 (24)",
"str x6, [x8]",
"str x5, [x8]",
"ldrb w14, [x11]",
"add x20, x14, x14, lsl #2",
"mov w5, w20",
"mov w7, w20",
"ldrb w4, [x10]",
"add w4, w4, w5",
"add w4, w4, w7",
"mvn w27, w4",
"subs w26, w4, #0x18 (24)"
]
@@ -306,8 +306,8 @@
"cmp dword [rbx+r10*4+0xc],0xffffffff"
],
"ExpectedArm64ASM": [
"mov x13, x6",
"mov x12, x5",
"mov x13, x5",
"mov x12, x7",
"mov w14, w10",
"lsr w14, w14, #3",
"ldrb w14, [x9, x14, sxtx]",
@@ -317,16 +317,16 @@
"eor x20, x20, #0x1",
"rmif x20, #63, #nzCv",
"add x12, x12, x12, lsl #2",
"add x20, x7, #0x10 (16)",
"add x20, x6, #0x10 (16)",
"add x12, x20, x12, lsl #2",
"csel x12, x13, x12, hs",
"ldr w20, [x12]",
"sxtw x12, w20",
"add x10, x10, #0x1 (1)",
"add x14, x12, x12, lsl #2",
"add x13, x7, x14, lsl #2",
"add x13, x6, x14, lsl #2",
"add x13, x13, #0xc (12)",
"add x20, x7, x14, lsl #2",
"add x20, x6, x14, lsl #2",
"ldr w20, [x20, #12]",
"mvn w27, w20",
"adds w26, w20, #0x1 (1)"
@@ -349,18 +349,18 @@
"ExpectedArm64ASM": [
"sxtw x13, w12",
"add x13, x13, x13, lsl #2",
"add x20, x7, x13, lsl #2",
"add x20, x6, x13, lsl #2",
"ldr w20, [x20, #12]",
"cmp w20, w5",
"cmp w20, w7",
"cset x20, eq",
"bfxil x5, x20, #0, #8",
"bfxil x7, x20, #0, #8",
"mov w20, #0x31",
"eor x5, x5, x20",
"eor x7, x7, x20",
"add x20, x8, x11",
"strb w5, [x20, #80]",
"strb w7, [x20, #80]",
"add x11, x11, #0x1 (1)",
"mov w5, w12",
"add x20, x7, x13, lsl #2",
"mov w7, w12",
"add x20, x6, x13, lsl #2",
"ldr w12, [x20, #8]",
"mvn w27, w12",
"adds w26, w12, #0x2 (2)"
@@ -390,19 +390,19 @@
"add rdi,0xffffffffffffffff"
],
"ExpectedArm64ASM": [
"mov w5, w4",
"and x5, x5, #0xffffffffffffff07",
"mov w7, w4",
"and x7, x7, #0xffffffffffffff07",
"mov w20, #0x1",
"bfxil x12, x20, #0, #8",
"lsl w20, w12, w5",
"lsl w20, w12, w7",
"bfxil x12, x20, #0, #8",
"mov w13, w4",
"lsr w13, w13, #3",
"ldrb w14, [x9, x13, sxtx]",
"mov w20, #0xfe",
"bfxil x15, x20, #0, #8",
"mov w5, w4",
"and x20, x5, #0x7",
"mov w7, w4",
"and x20, x7, #0x7",
"mov w21, w15",
"bfi w21, w15, #24, #8",
"neg w20, w20",
@@ -417,9 +417,9 @@
"ldrb w21, [x21, #79]",
"lsl w0, w21, #24",
"cmp w0, w20, lsl #24",
"uxtb w5, w12",
"uxtb w7, w12",
"uxtb w12, w15",
"csel w12, w5, w12, eq",
"csel w12, w7, w12, eq",
"add x4, x4, #0x1 (1)",
"strb w12, [x9, x13, sxtx]",
"mvn w27, w11",
@@ -456,25 +456,25 @@
"ldp q21, q2, [x10, #32]",
"ldp q22, q3, [x10, #64]",
"sub x20, x11, #0x81 (129)",
"add x5, x20, x6",
"add x7, x20, x5",
"ldp q23, q4, [x10, #96]",
"add x20, x10, x6",
"add x20, x10, x5",
"ldp q24, q5, [x20, #-32]",
"sub x10, x10, x11",
"and x5, x5, #0xffffffffffffffe0",
"add x10, x10, x5",
"and x7, x7, #0xffffffffffffffe0",
"add x10, x10, x7",
"ldp q17, q6, [x10, #96]",
"ldp q18, q7, [x10, #64]",
"ldp q19, q8, [x10, #32]",
"ldp q20, q9, [x10]",
"sub x10, x10, #0x80 (128)",
"stp q17, q6, [x5, #96]",
"stp q18, q7, [x5, #64]",
"stp q19, q8, [x5, #32]",
"stp q20, q9, [x5]",
"sub x5, x5, #0x80 (128)",
"eor w27, w11, w5",
"subs x26, x11, x5",
"stp q17, q6, [x7, #96]",
"stp q18, q7, [x7, #64]",
"stp q19, q8, [x7, #32]",
"stp q20, q9, [x7]",
"sub x7, x7, #0x80 (128)",
"eor w27, w11, w7",
"subs x26, x11, x7",
"stp q4, q5, [x28, #128]",
"stp q2, q3, [x28, #96]",
"stp q8, q9, [x28, #64]",
@@ -508,21 +508,21 @@
"cmp rdx,rdi"
],
"ExpectedArm64ASM": [
"add x20, x10, x6",
"add x20, x10, x5",
"ldp q21, q2, [x20, #-32]",
"add x20, x10, x6",
"add x20, x10, x5",
"ldp q22, q3, [x20, #-64]",
"mov x5, x11",
"mov x7, x11",
"orr x11, x11, #0x1f",
"add x20, x10, x6",
"add x20, x10, x5",
"ldp q23, q4, [x20, #-96]",
"add x20, x10, x6",
"add x20, x10, x5",
"ldp q24, q5, [x20, #-128]",
"sub x10, x10, x5",
"sub x10, x10, x7",
"add x11, x11, #0x1 (1)",
"add x10, x10, x11",
"sub x20, x5, #0x80 (128)",
"add x6, x20, x6",
"sub x20, x7, #0x80 (128)",
"add x5, x20, x5",
"ldp q17, q6, [x10]",
"ldp q18, q7, [x10, #32]",
"ldp q19, q8, [x10, #64]",
@@ -533,8 +533,8 @@
"stp q19, q8, [x11, #64]",
"stp q20, q9, [x11, #96]",
"add x11, x11, #0x80 (128)",
"eor w27, w6, w11",
"subs x26, x6, x11",
"eor w27, w5, w11",
"subs x26, x5, x11",
"stp q4, q5, [x28, #128]",
"stp q2, q3, [x28, #96]",
"stp q8, q9, [x28, #64]",
@@ -561,9 +561,9 @@
"cmp rsi,r8"
],
"ExpectedArm64ASM": [
"mov x10, x6",
"mov x10, x5",
"and x10, x10, #0xfffffffffffffffc",
"fmov d16, x5",
"fmov d16, x7",
"dup v16.2d, v16.d[0]",
"ldr x11, [x8, #32]",
"add x11, x11, x17, lsl #3",
@@ -592,8 +592,8 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -610,8 +610,8 @@
"blr x5",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -627,7 +627,7 @@
"clz w23, w0",
"csinv w23, w23, wzr, ne",
"cmp x21, #0x0 (0)",
"csel x5, x22, x23, eq",
"csel x7, x22, x23, eq",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+73 -75
View File
@@ -28,21 +28,21 @@
"cmp esi, ebx"
],
"ExpectedArm64ASM": [
"add w20, w10, w5",
"ldrb w6, [x20]",
"add w20, w10, w11",
"add w20, w10, w7",
"ldrb w5, [x20]",
"orr w6, w6, #0xffff0000",
"lsl w6, w6, #8",
"add w20, w10, w11",
"ldrb w7, [x20]",
"orr w5, w5, #0xffff0000",
"lsl w5, w5, #8",
"add w10, w10, #0x1 (1)",
"orr w6, w6, w5",
"ldr w5, [x9, #12]",
"orr w5, w5, w7",
"ldr w7, [x9, #12]",
"ldr w20, [x4]",
"orr w20, w20, w6",
"orr w20, w20, w5",
"str w20, [x4]",
"add w4, w4, #0x4 (4)",
"eor w27, w10, w7",
"subs w26, w10, w7"
"eor w27, w10, w6",
"subs w26, w10, w6"
]
},
"wine mscrt.dll memmove": {
@@ -73,13 +73,13 @@
"str q19, [x11, #48]",
"add w10, w10, #0x40 (64)",
"add w11, w11, #0x40 (64)",
"sub w5, w5, #0x40 (64)",
"subs w26, w5, #0x40 (64)",
"mov x27, x5"
"sub w7, w7, #0x40 (64)",
"subs w26, w7, #0x40 (64)",
"mov x27, x7"
]
},
"dxvk hotblock from MGRR": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 27,
"Comment": [
"Hottest block in Metal Gear Rising: Revengeance render thread"
],
@@ -100,34 +100,32 @@
"lock cmpxchg8b qword [esi+0x8]"
],
"ExpectedArm64ASM": [
"ldr w6, [x4, #12]",
"ldr w5, [x4, #12]",
"ldr w4, [x4, #8]",
"stur w10, [x9, #-52]",
"mov x5, x4",
"mov x7, x6",
"mov x7, x4",
"mov x6, x5",
"ldur w10, [x9, #-36]",
"mov w20, #0xffffffff",
"subs w5, w5, #0x1 (1)",
"mvn w27, w7",
"adcs w26, w7, w20",
"mov x7, x26",
"stur w5, [x9, #-40]",
"stur w7, [x9, #-44]",
"mov x7, x5",
"stur w5, [x9, #-48]",
"ldur w5, [x9, #-44]",
"subs w7, w7, #0x1 (1)",
"mvn w27, w6",
"adcs w26, w6, w20",
"mov x6, x26",
"stur w7, [x9, #-40]",
"stur w6, [x9, #-44]",
"mov x6, x7",
"stur w7, [x9, #-48]",
"ldur w7, [x9, #-44]",
"add w20, w10, #0x8 (8)",
"mov x0, x7",
"mov x1, x5",
"mov x22, x4",
"mov x23, x6",
"caspal w22, w23, w0, w1, [x20]",
"mov x23, x5",
"caspal w22, w23, w6, w7, [x20]",
"mrs x0, nzcv",
"cmp w22, w4",
"ccmp w23, w6, #nzcv, eq",
"ccmp w23, w5, #nzcv, eq",
"rmif x0, #0, #NzCV",
"csel x4, x22, x4, ne",
"csel x6, x23, x6, ne",
"csel x5, x23, x5, ne",
"cfinv"
]
},
@@ -249,133 +247,133 @@
"subs w26, w8, #0x44 (68)",
"mov x27, x8",
"mov x8, x26",
"stur w5, [x9, #-68]",
"stur w7, [x9, #-68]",
"ldur w4, [x9, #-68]",
"ldr s2, [x4]",
"sub w20, w9, #0x40 (64)",
"str s2, [x20]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #16]",
"ldur w7, [x9, #-68]",
"ldr s2, [x7, #16]",
"sub w20, w9, #0x3c (60)",
"str s2, [x20]",
"ldur w6, [x9, #-68]",
"ldr s2, [x6, #32]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #32]",
"sub w20, w9, #0x38 (56)",
"str s2, [x20]",
"ldur w4, [x9, #-68]",
"ldr s2, [x4, #48]",
"sub w20, w9, #0x34 (52)",
"str s2, [x20]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #4]",
"ldur w7, [x9, #-68]",
"ldr s2, [x7, #4]",
"sub w20, w9, #0x30 (48)",
"str s2, [x20]",
"ldur w6, [x9, #-68]",
"ldr s2, [x6, #20]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #20]",
"sub w20, w9, #0x2c (44)",
"str s2, [x20]",
"ldur w4, [x9, #-68]",
"ldr s2, [x4, #36]",
"sub w20, w9, #0x28 (40)",
"str s2, [x20]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #52]",
"ldur w7, [x9, #-68]",
"ldr s2, [x7, #52]",
"sub w20, w9, #0x24 (36)",
"str s2, [x20]",
"ldur w6, [x9, #-68]",
"ldr s2, [x6, #8]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #8]",
"sub w20, w9, #0x20 (32)",
"str s2, [x20]",
"ldur w4, [x9, #-68]",
"ldr s2, [x4, #24]",
"sub w20, w9, #0x1c (28)",
"str s2, [x20]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #40]",
"ldur w7, [x9, #-68]",
"ldr s2, [x7, #40]",
"sub w20, w9, #0x18 (24)",
"str s2, [x20]",
"ldur w6, [x9, #-68]",
"ldr s2, [x6, #56]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #56]",
"sub w20, w9, #0x14 (20)",
"str s2, [x20]",
"ldur w4, [x9, #-68]",
"ldr s2, [x4, #12]",
"sub w20, w9, #0x10 (16)",
"str s2, [x20]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #28]",
"ldur w7, [x9, #-68]",
"ldr s2, [x7, #28]",
"sub w20, w9, #0xc (12)",
"str s2, [x20]",
"ldur w6, [x9, #-68]",
"ldr s2, [x6, #44]",
"ldur w5, [x9, #-68]",
"ldr s2, [x5, #44]",
"sub w20, w9, #0x8 (8)",
"str s2, [x20]",
"ldur w4, [x9, #-68]",
"ldr s2, [x4, #60]",
"sub w20, w9, #0x4 (4)",
"str s2, [x20]",
"ldr w5, [x9, #8]",
"ldr w7, [x9, #8]",
"ldur s2, [x9, #-64]",
"str s2, [x5]",
"ldr w6, [x9, #8]",
"str s2, [x7]",
"ldr w5, [x9, #8]",
"ldur s2, [x9, #-60]",
"add w20, w6, #0x4 (4)",
"add w20, w5, #0x4 (4)",
"str s2, [x20]",
"ldr w4, [x9, #8]",
"ldur s2, [x9, #-56]",
"add w20, w4, #0x8 (8)",
"str s2, [x20]",
"ldr w5, [x9, #8]",
"ldr w7, [x9, #8]",
"ldur s2, [x9, #-52]",
"add w20, w5, #0xc (12)",
"add w20, w7, #0xc (12)",
"str s2, [x20]",
"ldr w6, [x9, #8]",
"ldr w5, [x9, #8]",
"ldur s2, [x9, #-48]",
"add w20, w6, #0x10 (16)",
"add w20, w5, #0x10 (16)",
"str s2, [x20]",
"ldr w4, [x9, #8]",
"ldur s2, [x9, #-44]",
"add w20, w4, #0x14 (20)",
"str s2, [x20]",
"ldr w5, [x9, #8]",
"ldr w7, [x9, #8]",
"ldur s2, [x9, #-40]",
"add w20, w5, #0x18 (24)",
"add w20, w7, #0x18 (24)",
"str s2, [x20]",
"ldr w6, [x9, #8]",
"ldr w5, [x9, #8]",
"ldur s2, [x9, #-36]",
"add w20, w6, #0x1c (28)",
"add w20, w5, #0x1c (28)",
"str s2, [x20]",
"ldr w4, [x9, #8]",
"ldur s2, [x9, #-32]",
"add w20, w4, #0x20 (32)",
"str s2, [x20]",
"ldr w5, [x9, #8]",
"ldr w7, [x9, #8]",
"ldur s2, [x9, #-28]",
"add w20, w5, #0x24 (36)",
"add w20, w7, #0x24 (36)",
"str s2, [x20]",
"ldr w6, [x9, #8]",
"ldr w5, [x9, #8]",
"ldur s2, [x9, #-24]",
"add w20, w6, #0x28 (40)",
"add w20, w5, #0x28 (40)",
"str s2, [x20]",
"ldr w4, [x9, #8]",
"ldur s2, [x9, #-20]",
"add w20, w4, #0x2c (44)",
"str s2, [x20]",
"ldr w5, [x9, #8]",
"ldr w7, [x9, #8]",
"ldur s2, [x9, #-16]",
"add w20, w5, #0x30 (48)",
"add w20, w7, #0x30 (48)",
"str s2, [x20]",
"ldr w6, [x9, #8]",
"ldr w5, [x9, #8]",
"ldur s2, [x9, #-12]",
"add w20, w6, #0x34 (52)",
"add w20, w5, #0x34 (52)",
"str s2, [x20]",
"ldr w4, [x9, #8]",
"ldur s2, [x9, #-8]",
"add w20, w4, #0x38 (56)",
"str s2, [x20]",
"ldr w5, [x9, #8]",
"ldr w7, [x9, #8]",
"ldur s2, [x9, #-4]",
"add w20, w5, #0x3c (60)",
"add w20, w7, #0x3c (60)",
"str s2, [x20]",
"ldr w4, [x9, #8]",
"mov x8, x9",
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+12 -12
View File
@@ -55,47 +55,47 @@
"sub esi, 0x1"
],
"ExpectedArm64ASM": [
"mov w10, w5",
"mov x6, x9",
"mov x4, x7",
"ldr s18, [x6]",
"mov w10, w7",
"mov x5, x9",
"mov x4, x6",
"ldr s18, [x5]",
"add x4, x4, #0x20 (32)",
"fmul s18, s18, s16",
"add x6, x6, #0x20 (32)",
"add x5, x5, #0x20 (32)",
"ldur s2, [x4, #-32]",
"fadd s18, s18, s2",
"stur s18, [x4, #-32]",
"ldur s18, [x6, #-28]",
"ldur s18, [x5, #-28]",
"fmul s18, s18, s17",
"ldur s2, [x4, #-28]",
"fadd s18, s18, s2",
"stur s18, [x4, #-28]",
"ldur s18, [x6, #-24]",
"ldur s18, [x5, #-24]",
"fmul s18, s18, s16",
"ldur s2, [x4, #-24]",
"fadd s18, s18, s2",
"stur s18, [x4, #-24]",
"ldur s18, [x6, #-20]",
"ldur s18, [x5, #-20]",
"fmul s18, s18, s17",
"ldur s2, [x4, #-20]",
"fadd s18, s18, s2",
"stur s18, [x4, #-20]",
"ldur s18, [x6, #-16]",
"ldur s18, [x5, #-16]",
"fmul s18, s18, s16",
"ldur s2, [x4, #-16]",
"fadd s18, s18, s2",
"stur s18, [x4, #-16]",
"ldur s18, [x6, #-12]",
"ldur s18, [x5, #-12]",
"fmul s18, s18, s17",
"ldur s2, [x4, #-12]",
"fadd s18, s18, s2",
"stur s18, [x4, #-12]",
"ldur s18, [x6, #-8]",
"ldur s18, [x5, #-8]",
"fmul s18, s18, s16",
"ldur s2, [x4, #-8]",
"fadd s18, s18, s2",
"stur s18, [x4, #-8]",
"ldur s18, [x6, #-4]",
"ldur s18, [x5, #-4]",
"fmul s18, s18, s17",
"ldur s2, [x4, #-4]",
"fadd s18, s18, s2",
unittests/InstructionCountCI/FlagM/Primary.json
+367 -367
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+114 -114
View File
@@ -1609,13 +1609,13 @@
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd2 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x7",
"and x20, x7, #0x7",
"mov w21, w4",
"bfi w21, w4, #24, #8",
"neg w20, w20",
"ror w20, w21, w20",
"bfxil x4, x20, #0, #8",
"and x21, x5, #0x1f",
"and x21, x7, #0x1f",
"cbz w21, #+0x14",
"eor x0, x20, x20, lsr #7",
"mvn x1, x20",
@@ -1627,12 +1627,12 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x7",
"and x20, x7, #0x7",
"mov w21, w4",
"bfi w21, w4, #8, #8",
"ror w20, w21, w20",
"bfxil x4, x20, #0, #8",
"and x21, x5, #0x1f",
"and x21, x7, #0x1f",
"cbz w21, #+0x14",
"eor x0, x20, x20, lsr #1",
"mvn x1, x20",
@@ -1644,9 +1644,9 @@
"ExpectedInstructionCount": 27,
"Comment": "GROUP2 0xd2 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x68",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -1677,9 +1677,9 @@
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd2 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x40",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cset w21, lo",
"uxtb w22, w4",
"bfi x22, x21, #8, #1",
@@ -1700,8 +1700,8 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"lsl w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x1c",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
@@ -1717,12 +1717,12 @@
"Comment": "GROUP2 0xd2 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w21, w20, w5",
"and w0, w5, #0x1f",
"lsr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x24",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"eor w2, w20, w21",
@@ -1736,12 +1736,12 @@
"Comment": "GROUP2 0xd2 /7",
"ExpectedArm64ASM": [
"sxtb x20, w4",
"asr w21, w20, w5",
"and w0, w5, #0x1f",
"asr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x1c",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"rmif x0, #63, #nzCv",
@@ -1752,7 +1752,7 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"mov w21, w4",
"bfi w21, w4, #16, #16",
"neg w22, w20",
@@ -1769,7 +1769,7 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"neg w21, w20",
"ror w4, w4, w21",
"cbz w20, #+0x14",
@@ -1783,7 +1783,7 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"neg x21, x20",
"ror x4, x4, x21",
"cbz x20, #+0x14",
@@ -1797,7 +1797,7 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"mov w21, w4",
"bfi w21, w4, #16, #16",
"ror w21, w21, w20",
@@ -1813,7 +1813,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"ror w4, w4, w20",
"cbz w20, #+0x14",
"eor x0, x4, x4, lsr #1",
@@ -1826,7 +1826,7 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"ror x4, x4, x20",
"cbz x20, #+0x14",
"eor x0, x4, x4, lsr #1",
@@ -1839,9 +1839,9 @@
"ExpectedInstructionCount": 23,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x58",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -1868,17 +1868,17 @@
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x3c",
"lsl w20, w4, w5",
"lsl w20, w4, w7",
"cset w21, lo",
"neg w22, w5",
"neg w22, w7",
"lsr w23, w4, w22",
"orr w20, w20, w23, lsr #1",
"lsr w22, w4, w22",
"eor x23, x22, #0x1",
"rmif x23, #63, #nzCv",
"sub w23, w5, #0x1 (1)",
"sub w23, w7, #0x1 (1)",
"lsl w21, w21, w23",
"orr w4, w20, w21",
"eor w20, w4, w22, lsl #31",
@@ -1891,17 +1891,17 @@
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"cbz x20, #+0x38",
"lsl x20, x4, x5",
"lsl x20, x4, x7",
"cset w21, lo",
"neg x22, x5",
"neg x22, x7",
"lsr x23, x4, x22",
"orr x20, x20, x23, lsr #1",
"lsr x22, x4, x22",
"eor x23, x22, #0x1",
"rmif x23, #63, #nzCv",
"sub x23, x5, #0x1 (1)",
"sub x23, x7, #0x1 (1)",
"lsl x21, x21, x23",
"orr x4, x20, x21",
"eor x20, x4, x22, lsl #63",
@@ -1912,9 +1912,9 @@
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x3c",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cset w21, lo",
"uxth w22, w4",
"bfi x22, x21, #16, #1",
@@ -1934,14 +1934,14 @@
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x3c",
"lsr w20, w4, w5",
"lsr w20, w4, w7",
"cset w21, lo",
"neg w22, w5",
"neg w22, w7",
"lsl w23, w4, w22",
"orr w20, w20, w23, lsl #1",
"sub w23, w5, #0x1 (1)",
"sub w23, w7, #0x1 (1)",
"lsr w23, w4, w23",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
@@ -1957,14 +1957,14 @@
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"cbz x20, #+0x38",
"lsr x20, x4, x5",
"lsr x20, x4, x7",
"cset w21, lo",
"neg x22, x5",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
"sub x23, x5, #0x1 (1)",
"sub x23, x7, #0x1 (1)",
"lsr x23, x4, x23",
"eor x23, x23, #0x1",
"rmif x23, #63, #nzCv",
@@ -1978,8 +1978,8 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"lsl w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x1c",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
@@ -1994,11 +1994,11 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"lsl w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x20",
"ands w26, w20, w20",
"neg w0, w5",
"neg w0, w7",
"lsr w0, w4, w0",
"mvn x0, x0",
"eor w2, w4, w20",
@@ -2011,11 +2011,11 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl x20, x4, x5",
"and w0, w5, #0x3f",
"lsl x20, x4, x7",
"and w0, w7, #0x3f",
"cbz x0, #+0x20",
"ands x26, x20, x20",
"neg x0, x5",
"neg x0, x7",
"lsr x0, x4, x0",
"mvn x0, x0",
"eor x2, x4, x20",
@@ -2029,12 +2029,12 @@
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, w5",
"and w0, w5, #0x1f",
"lsr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x24",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"eor w2, w20, w21",
@@ -2047,11 +2047,11 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"lsr w20, w4, w5",
"and w0, w5, #0x1f",
"lsr w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x20",
"ands w26, w20, w20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w4, w0",
"mvn x0, x0",
"eor w2, w4, w20",
@@ -2064,11 +2064,11 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"lsr x20, x4, x5",
"and w0, w5, #0x3f",
"lsr x20, x4, x7",
"and w0, w7, #0x3f",
"cbz x0, #+0x20",
"ands x26, x20, x20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr x0, x4, x0",
"mvn x0, x0",
"eor x2, x4, x20",
@@ -2082,12 +2082,12 @@
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"sxth x20, w4",
"asr w21, w20, w5",
"and w0, w5, #0x1f",
"asr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x1c",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"rmif x0, #63, #nzCv",
@@ -2098,11 +2098,11 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"asr w20, w4, w5",
"and w0, w5, #0x1f",
"asr w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x18",
"ands w26, w20, w20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w4, w0",
"mvn x0, x0",
"rmif x0, #63, #nzCv",
@@ -2113,11 +2113,11 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"asr x20, x4, x5",
"and w0, w5, #0x3f",
"asr x20, x4, x7",
"and w0, w7, #0x3f",
"cbz x0, #+0x18",
"ands x26, x20, x20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr x0, x4, x0",
"mvn x0, x0",
"rmif x0, #63, #nzCv",
@@ -2128,7 +2128,7 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf6 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0x1",
"and w26, w6, #0x1",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -2137,26 +2137,26 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"eor x7, x7, #0xff"
"eor x6, x6, #0xff"
]
},
"neg bl": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"mov x20, x7",
"cmp wzr, w6, lsl #24",
"neg w26, w6",
"mov x20, x6",
"bfxil x20, x26, #0, #8",
"mov x27, x7",
"mov x7, x20"
"mov x27, x6",
"mov x6, x20"
]
},
"mul bl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf6 /4",
"ExpectedArm64ASM": [
"uxtb x20, w7",
"uxtb x20, w6",
"uxtb x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
@@ -2169,7 +2169,7 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf6 /5",
"ExpectedArm64ASM": [
"sxtb x20, w7",
"sxtb x20, w6",
"sxtb x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
@@ -2183,7 +2183,7 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xf6 /6",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w20, w6",
"uxth w21, w4",
"uxth w0, w21",
"uxth w1, w20",
@@ -2200,7 +2200,7 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /7",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w20, w6",
"uxth w21, w4",
"sxth x21, w21",
"sxtb x20, w20",
@@ -2215,7 +2215,7 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0x1",
"and w26, w6, #0x1",
"cmn wzr, w26, lsl #16",
"cfinv"
]
@@ -2224,7 +2224,7 @@
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w7, #0x1",
"ands w26, w6, #0x1",
"cfinv"
]
},
@@ -2232,7 +2232,7 @@
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x7, #0x1",
"ands x26, x6, #0x1",
"cfinv"
]
},
@@ -2240,7 +2240,7 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x26, x7",
"mov x26, x6",
"cmn wzr, w26, lsl #16",
"cfinv"
]
@@ -2249,7 +2249,7 @@
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w7, w7",
"ands w26, w6, w6",
"cfinv"
]
},
@@ -2257,7 +2257,7 @@
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x7, x7",
"ands x26, x6, x6",
"cfinv"
]
},
@@ -2265,42 +2265,42 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"mov x20, x7",
"cmp wzr, w6, lsl #16",
"neg w26, w6",
"mov x20, x6",
"bfxil x20, x26, #0, #16",
"mov x27, x7",
"mov x7, x20"
"mov x27, x6",
"mov x6, x20"
]
},
"neg ebx": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"negs w26, w7",
"mov x27, x7",
"mov x7, x26"
"negs w26, w6",
"mov x27, x6",
"mov x6, x26"
]
},
"neg rbx": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"negs x26, x7",
"mov x27, x7",
"mov x7, x26"
"negs x26, x6",
"mov x27, x6",
"mov x6, x26"
]
},
"mul bx": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"uxth x20, w7",
"uxth x20, w6",
"uxth x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"ubfx x20, x20, #16, #16",
"bfxil x6, x20, #0, #16",
"bfxil x5, x20, #0, #16",
"cmp x20, #0x0 (0)",
"ccmp xzr, #0, #nzcV, eq"
]
@@ -2309,12 +2309,12 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"mov w21, w4",
"mul x20, x20, x21",
"mov w4, w20",
"lsr x6, x20, #32",
"cmp x6, #0x0 (0)",
"lsr x5, x20, #32",
"cmp x5, #0x0 (0)",
"ccmp xzr, #0, #nzcV, eq"
]
},
@@ -2322,9 +2322,9 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"cmp x6, #0x0 (0)",
"mul x20, x6, x4",
"umulh x5, x6, x4",
"cmp x5, #0x0 (0)",
"ccmp xzr, #0, #nzcV, eq",
"mov x4, x20"
]
@@ -2333,12 +2333,12 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"sxth x20, w7",
"sxth x20, w6",
"sxth x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"sbfx x21, x20, #16, #16",
"bfxil x6, x21, #0, #16",
"bfxil x5, x21, #0, #16",
"sbfx x20, x20, #15, #1",
"cmp x21, x20",
"ccmp xzr, #0, #nzcV, eq"
@@ -2348,11 +2348,11 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"sxtw x20, w7",
"sxtw x20, w6",
"sxtw x21, w4",
"mul x20, x20, x21",
"mov w4, w20",
"lsr x6, x20, #32",
"lsr x5, x20, #32",
"asr x21, x20, #32",
"sxtw x20, w20",
"sbfx x20, x20, #31, #1",
@@ -2364,10 +2364,10 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"smulh x6, x7, x4",
"mul x4, x7, x4",
"smulh x5, x6, x4",
"mul x4, x6, x4",
"asr x20, x4, #63",
"cmp x6, x20",
"cmp x5, x20",
"ccmp xzr, #0, #nzcV, eq"
]
},
@@ -2375,9 +2375,9 @@
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xf7 /6",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"uxth w21, w4",
"uxth w22, w6",
"uxth w22, w5",
"uxth w0, w21",
"bfi w0, w22, #16, #16",
"udiv w23, w0, w20",
@@ -2386,7 +2386,7 @@
"udiv w1, w0, w20",
"msub w20, w1, w20, w0",
"bfxil x4, x23, #0, #16",
"bfxil x6, x20, #0, #16"
"bfxil x5, x20, #0, #16"
]
},
"inc al": {
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+4 -4
View File
@@ -246,9 +246,9 @@
"ExpectedArm64ASM": [
"mov w20, w8",
"str w4, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
@@ -262,9 +262,9 @@
"ExpectedArm64ASM": [
"mov w20, w8",
"str w4, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
@@ -282,9 +282,9 @@
"ldr w9, [x20], #4",
"add x20, x20, #0x4 (4)",
"mov x8, x20",
"ldr w7, [x8], #4",
"ldr w6, [x8], #4",
"ldr w5, [x8], #4",
"ldr w7, [x8], #4",
"ldr w4, [x8], #4"
]
},
@@ -298,9 +298,9 @@
"ldr w9, [x20], #4",
"add x20, x20, #0x4 (4)",
"mov x8, x20",
"ldr w7, [x8], #4",
"ldr w6, [x8], #4",
"ldr w5, [x8], #4",
"ldr w7, [x8], #4",
"ldr w4, [x8], #4"
]
},
unittests/InstructionCountCI/FlagM/Secondary.json
+183 -183
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+10 -14
View File
@@ -705,37 +705,33 @@
]
},
"cmpxchg8b [rbp]": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x20, x4",
"mov x21, x6",
"caspal w20, w21, w0, w1, [x9]",
"mov x21, x5",
"caspal w20, w21, w6, w7, [x9]",
"mrs x0, nzcv",
"cmp w20, w4",
"ccmp w21, w6, #nzcv, eq",
"ccmp w21, w5, #nzcv, eq",
"rmif x0, #0, #NzCV",
"csel x4, x20, x4, ne",
"csel x6, x21, x6, ne"
"csel x5, x21, x5, ne"
]
},
"cmpxchg16b [rbp]": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x20, x4",
"mov x21, x6",
"caspal x20, x21, x0, x1, [x9]",
"mov x21, x5",
"caspal x20, x21, x6, x7, [x9]",
"mrs x0, nzcv",
"cmp x20, x4",
"ccmp x21, x6, #nzcv, eq",
"ccmp x21, x5, #nzcv, eq",
"rmif x0, #0, #NzCV",
"csel x4, x20, x4, ne",
"csel x6, x21, x6, ne"
"csel x5, x21, x5, ne"
]
},
"rdrand ax": {
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+8 -8
View File
@@ -26,8 +26,8 @@
"str x30, [x3]",
"mrs x3, nzcv",
"str w3, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -41,7 +41,7 @@
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
"mov w1, w5",
"mov w1, w7",
"ldr x0, [x28, #1368]",
"ldr x2, [x28, #1384]",
"blr x2",
@@ -52,8 +52,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -68,7 +68,7 @@
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov w4, w0",
"lsr x6, x0, #32"
"lsr x5, x0, #32"
]
},
"rdtscp": {
@@ -78,7 +78,7 @@
"dmb ld",
"mrs x20, S3_3_c14_c0_2",
"lsl w4, w20, #7",
"lsr x6, x20, #25",
"lsr x5, x20, #25",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
@@ -95,7 +95,7 @@
"msr nzcv, x8",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x5, x0, x1, lsl #12"
"orr x7, x0, x1, lsl #12"
]
}
}
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+9 -9
View File
@@ -17,7 +17,7 @@
"ExpectedInstructionCount": 9,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addp v0.8b, v0.8b, v0.8b",
@@ -32,7 +32,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov s0, w7",
"fmov s0, w6",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
@@ -45,7 +45,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"fmov d0, x6",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
@@ -58,7 +58,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w20, w7",
"rbit w20, w6",
"orr w20, w20, #0x8000",
"clz w20, w20",
"bfxil x4, x20, #0, #16",
@@ -71,7 +71,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w4, w7",
"rbit w4, w6",
"clz w4, w4",
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
@@ -82,7 +82,7 @@
"ExpectedInstructionCount": 5,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x4, x7",
"rbit x4, x6",
"clz x4, x4",
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
@@ -93,7 +93,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"lsl w20, w7, #16",
"lsl w20, w6, #16",
"orr w20, w20, #0x8000",
"clz w20, w20",
"bfxil x4, x20, #0, #16",
@@ -106,7 +106,7 @@
"ExpectedInstructionCount": 4,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz w4, w7",
"clz w4, w6",
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
"rmif x20, #4, #nzCv"
@@ -116,7 +116,7 @@
"ExpectedInstructionCount": 4,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz x4, x7",
"clz x4, x6",
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
"rmif x20, #5, #nzCv"
unittests/InstructionCountCI/FlagM/VEX_map2.json
+22 -22
View File
@@ -350,7 +350,7 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"bic w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x4, x26"
]
@@ -361,7 +361,7 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"bic x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x4, x26"
]
@@ -373,10 +373,10 @@
],
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"lsl w20, w20, w5",
"bic w20, w7, w20",
"tst x5, #0xe0",
"csel w4, w7, w20, ne",
"lsl w20, w20, w7",
"bic w20, w6, w20",
"tst x7, #0xe0",
"csel w4, w6, w20, ne",
"cset w20, eq",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -389,10 +389,10 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"lsl x20, x20, x5",
"bic x20, x7, x20",
"tst x5, #0xc0",
"csel x4, x7, x20, ne",
"lsl x20, x20, x7",
"bic x20, x6, x20",
"tst x7, #0xc0",
"csel x4, x6, x20, ne",
"cset w20, eq",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -404,10 +404,10 @@
"Map 2 0b11 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x0, x6",
"mov x1, x7",
"mov w4, #0x0",
"cbz w5, #+0x2c",
"cbz w7, #+0x2c",
"neg w2, w1",
"and w2, w2, w1",
"sbfx w3, w0, #0, #1",
@@ -426,10 +426,10 @@
"Map 2 0b11 0xf5 64-bit"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x0, x6",
"mov x1, x7",
"mov x4, #0x0",
"cbz x5, #+0x2c",
"cbz x7, #+0x2c",
"neg x2, x1",
"and x2, x2, x1",
"sbfx x3, x0, #0, #1",
@@ -448,12 +448,12 @@
"Map 2 0b00 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"uxtb w20, w5",
"lsr w21, w7, w20",
"uxtb w20, w7",
"lsr w21, w6, w20",
"mov w22, #0x0",
"cmp w20, #0x1f (31)",
"csel w20, w21, w22, ls",
"ubfx w21, w5, #8, #8",
"ubfx w21, w7, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl w22, w22, w21",
"bic w22, w20, w22",
@@ -468,12 +468,12 @@
"Map 2 0b00 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"uxtb x20, w5",
"lsr x21, x7, x20",
"uxtb x20, w7",
"lsr x21, x6, x20",
"mov w22, #0x0",
"cmp x20, #0x3f (63)",
"csel x20, x21, x22, ls",
"ubfx x21, x5, #8, #8",
"ubfx x21, x7, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl x22, x22, x21",
"bic x22, x20, x22",
unittests/InstructionCountCI/FlagM/VEX_map_group.json
+16 -16
View File
@@ -17,9 +17,9 @@
"Map group 17 0b001 32-bit"
],
"ExpectedArm64ASM": [
"sub w20, w7, #0x1 (1)",
"and w4, w20, w7",
"cmp x7, #0x0 (0)",
"sub w20, w6, #0x1 (1)",
"and w4, w20, w6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -31,9 +31,9 @@
"Map group 17 0b001 64-bit"
],
"ExpectedArm64ASM": [
"sub x20, x7, #0x1 (1)",
"and x4, x20, x7",
"cmp x7, #0x0 (0)",
"sub x20, x6, #0x1 (1)",
"and x4, x20, x6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -45,9 +45,9 @@
"Map group 17 0b010 32-bit"
],
"ExpectedArm64ASM": [
"sub w20, w7, #0x1 (1)",
"eor w4, w20, w7",
"cmp x7, #0x0 (0)",
"sub w20, w6, #0x1 (1)",
"eor w4, w20, w6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -59,9 +59,9 @@
"Map group 17 0b010 64-bit"
],
"ExpectedArm64ASM": [
"sub x20, x7, #0x1 (1)",
"eor x4, x20, x7",
"cmp x7, #0x0 (0)",
"sub x20, x6, #0x1 (1)",
"eor x4, x20, x6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"rmif x20, #63, #nzCv"
@@ -73,8 +73,8 @@
"Map group 17 0b011 32-bit"
],
"ExpectedArm64ASM": [
"neg w20, w7",
"and w4, w7, w20",
"neg w20, w6",
"and w4, w6, w20",
"cmp w4, #0x0 (0)",
"cset w20, eq",
"rmif x20, #63, #nzCv"
@@ -86,8 +86,8 @@
"Map group 17 0b011 64-bit"
],
"ExpectedArm64ASM": [
"neg x20, x7",
"and x4, x7, x20",
"neg x20, x6",
"and x4, x6, x20",
"cmp x4, #0x0 (0)",
"cset w20, eq",
"rmif x20, #63, #nzCv"
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+818 -818
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+9502 -9502
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+14581 -14581
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+1253 -1253
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+144 -144
View File
@@ -2261,8 +2261,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2299,8 +2299,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2331,8 +2331,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2368,8 +2368,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2397,8 +2397,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2435,8 +2435,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2480,8 +2480,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2517,8 +2517,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2583,8 +2583,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2620,8 +2620,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2677,8 +2677,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2714,8 +2714,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2754,8 +2754,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2791,8 +2791,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2834,8 +2834,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2872,8 +2872,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2885,8 +2885,8 @@
"mov v3.8b, v0.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2923,8 +2923,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2980,8 +2980,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -3017,8 +3017,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -3043,8 +3043,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -3081,8 +3081,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -3108,8 +3108,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -3146,8 +3146,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -4116,8 +4116,8 @@
"ldr q2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -4132,8 +4132,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -4164,8 +4164,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -4179,8 +4179,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6344,8 +6344,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6360,8 +6360,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6376,8 +6376,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6392,8 +6392,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6408,8 +6408,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6424,8 +6424,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6440,8 +6440,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6456,8 +6456,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6472,8 +6472,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6488,8 +6488,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6504,8 +6504,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6520,8 +6520,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6536,8 +6536,8 @@
"and v2.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6552,8 +6552,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6569,8 +6569,8 @@
"mov v2.h[4], v3.h[0]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6585,8 +6585,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6671,8 +6671,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6686,8 +6686,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6703,8 +6703,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6718,8 +6718,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6735,8 +6735,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6750,8 +6750,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6767,8 +6767,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6782,8 +6782,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6799,8 +6799,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6814,8 +6814,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6831,8 +6831,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6846,8 +6846,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6863,8 +6863,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6878,8 +6878,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6895,8 +6895,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6910,8 +6910,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9412,8 +9412,8 @@
"ldr q2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9428,8 +9428,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9440,8 +9440,8 @@
"mov v2.h[4], w1",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9456,8 +9456,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9488,8 +9488,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9503,8 +9503,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9515,8 +9515,8 @@
"mov v2.h[4], w1",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9531,8 +9531,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -10095,15 +10095,15 @@
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str s2, [x6]",
"str s2, [x5]",
"ldr s2, [x4, #4]",
"add x20, x6, #0x4 (4)",
"add x20, x5, #0x4 (4)",
"str s2, [x20]",
"ldr s2, [x4, #8]",
"add x20, x6, #0x8 (8)",
"add x20, x5, #0x8 (8)",
"str s2, [x20]",
"ldr s2, [x4, #12]",
"add x20, x6, #0xc (12)",
"add x20, x5, #0xc (12)",
"str s2, [x20]",
"ldrb w20, [x28, #1019]",
"add w20, w20, #0x7 (7)",
@@ -10129,15 +10129,15 @@
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str d2, [x6]",
"str d2, [x5]",
"ldr d2, [x4, #8]",
"add x20, x6, #0x8 (8)",
"add x20, x5, #0x8 (8)",
"str d2, [x20]",
"ldr d2, [x4, #16]",
"add x20, x6, #0x10 (16)",
"add x20, x5, #0x10 (16)",
"str d2, [x20]",
"ldr d2, [x4, #32]",
"add x20, x6, #0x20 (32)",
"add x20, x5, #0x20 (32)",
"str d2, [x20]",
"ldrb w20, [x28, #1019]",
"add w20, w20, #0x7 (7)",
unittests/InstructionCountCI/H0F38.json
+11 -11
View File
@@ -832,7 +832,7 @@
"0x66 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"ldrh w20, [x7]",
"ldrh w20, [x6]",
"rev w20, w20",
"bfxil x4, x20, #16, #16"
]
@@ -843,7 +843,7 @@
"0x66 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"ldr w20, [x7]",
"ldr w20, [x6]",
"rev w4, w20"
]
},
@@ -853,7 +853,7 @@
"REX.W 0x66 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"ldr x20, [x7]",
"ldr x20, [x6]",
"rev x4, x20"
]
},
@@ -864,7 +864,7 @@
],
"ExpectedArm64ASM": [
"cset w20, lo",
"mov w21, w7",
"mov w21, w6",
"mov w22, w4",
"add w23, w21, w20",
"add w4, w22, w23",
@@ -887,12 +887,12 @@
],
"ExpectedArm64ASM": [
"cset w20, lo",
"add x21, x7, x20",
"add x21, x6, x20",
"add x4, x4, x21",
"mrs x21, nzcv",
"cmp x4, x7",
"cmp x4, x6",
"cset x22, lo",
"cmp x4, x7",
"cmp x4, x6",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
@@ -908,7 +908,7 @@
],
"ExpectedArm64ASM": [
"cset w20, vs",
"mov w21, w7",
"mov w21, w6",
"mov w22, w4",
"add w23, w21, w20",
"add w4, w22, w23",
@@ -930,12 +930,12 @@
],
"ExpectedArm64ASM": [
"cset w20, vs",
"add x21, x7, x20",
"add x21, x6, x20",
"add x4, x4, x21",
"mrs x21, nzcv",
"cmp x4, x7",
"cmp x4, x6",
"cset x22, lo",
"cmp x4, x7",
"cmp x4, x6",
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
unittests/InstructionCountCI/Primary.json
+499 -499
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/PrimaryGroup.json
+147 -147
View File
@@ -1900,13 +1900,13 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd2 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x7",
"and x20, x7, #0x7",
"mov w21, w4",
"bfi w21, w4, #24, #8",
"neg w20, w20",
"ror w20, w21, w20",
"bfxil x4, x20, #0, #8",
"and x21, x5, #0x1f",
"and x21, x7, #0x1f",
"cbz w21, #+0x1c",
"eor x0, x20, x20, lsr #7",
"mvn x1, x20",
@@ -1920,12 +1920,12 @@
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd2 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x7",
"and x20, x7, #0x7",
"mov w21, w4",
"bfi w21, w4, #8, #8",
"ror w20, w21, w20",
"bfxil x4, x20, #0, #8",
"and x21, x5, #0x1f",
"and x21, x7, #0x1f",
"cbz w21, #+0x24",
"eor x0, x20, x20, lsr #1",
"mvn x1, x20",
@@ -1941,9 +1941,9 @@
"ExpectedInstructionCount": 31,
"Comment": "GROUP2 0xd2 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x78",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -1978,9 +1978,9 @@
"ExpectedInstructionCount": 21,
"Comment": "GROUP2 0xd2 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x50",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cset w21, lo",
"uxtb w22, w4",
"bfi x22, x21, #8, #1",
@@ -2005,8 +2005,8 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"lsl w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x2c",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
@@ -2026,12 +2026,12 @@
"Comment": "GROUP2 0xd2 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsr w21, w20, w5",
"and w0, w5, #0x1f",
"lsr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x30",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"eor w2, w20, w21",
@@ -2048,12 +2048,12 @@
"Comment": "GROUP2 0xd2 /7",
"ExpectedArm64ASM": [
"sxtb x20, w4",
"asr w21, w20, w5",
"and w0, w5, #0x1f",
"asr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x24",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"mrs x1, nzcv",
@@ -2066,7 +2066,7 @@
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"mov w21, w4",
"bfi w21, w4, #16, #16",
"neg w22, w20",
@@ -2085,7 +2085,7 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"neg w21, w20",
"ror w4, w4, w21",
"cbz w20, #+0x1c",
@@ -2101,7 +2101,7 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"neg x21, x20",
"ror x4, x4, x21",
"cbz x20, #+0x1c",
@@ -2117,7 +2117,7 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"mov w21, w4",
"bfi w21, w4, #16, #16",
"ror w21, w21, w20",
@@ -2137,7 +2137,7 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x1f",
"and x20, x7, #0x1f",
"ror w4, w4, w20",
"cbz w20, #+0x24",
"eor x0, x4, x4, lsr #1",
@@ -2154,7 +2154,7 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /1",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"ror x4, x4, x20",
"cbz x20, #+0x24",
"eor x0, x4, x4, lsr #1",
@@ -2171,9 +2171,9 @@
"ExpectedInstructionCount": 27,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x68",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -2204,11 +2204,11 @@
"ExpectedInstructionCount": 21,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x4c",
"lsl w20, w4, w5",
"lsl w20, w4, w7",
"cset w21, lo",
"neg w22, w5",
"neg w22, w7",
"lsr w23, w4, w22",
"orr w20, w20, w23, lsr #1",
"lsr w22, w4, w22",
@@ -2216,7 +2216,7 @@
"ubfx x23, x23, #0, #1",
"mrs x24, nzcv",
"bfi w24, w23, #29, #1",
"sub w23, w5, #0x1 (1)",
"sub w23, w7, #0x1 (1)",
"lsl w21, w21, w23",
"orr w4, w20, w21",
"eor w20, w4, w22, lsl #31",
@@ -2231,11 +2231,11 @@
"ExpectedInstructionCount": 19,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"cbz x20, #+0x48",
"lsl x20, x4, x5",
"lsl x20, x4, x7",
"cset w21, lo",
"neg x22, x5",
"neg x22, x7",
"lsr x23, x4, x22",
"orr x20, x20, x23, lsr #1",
"lsr x22, x4, x22",
@@ -2243,7 +2243,7 @@
"ubfx x23, x23, #0, #1",
"mrs x24, nzcv",
"bfi w24, w23, #29, #1",
"sub x23, x5, #0x1 (1)",
"sub x23, x7, #0x1 (1)",
"lsl x21, x21, x23",
"orr x4, x20, x21",
"eor x20, x4, x22, lsl #63",
@@ -2256,9 +2256,9 @@
"ExpectedInstructionCount": 20,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x4c",
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cset w21, lo",
"uxth w22, w4",
"bfi x22, x21, #16, #1",
@@ -2282,14 +2282,14 @@
"ExpectedInstructionCount": 21,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"and w20, w7, #0x1f",
"cbz x20, #+0x4c",
"lsr w20, w4, w5",
"lsr w20, w4, w7",
"cset w21, lo",
"neg w22, w5",
"neg w22, w7",
"lsl w23, w4, w22",
"orr w20, w20, w23, lsl #1",
"sub w23, w5, #0x1 (1)",
"sub w23, w7, #0x1 (1)",
"lsr w23, w4, w23",
"eor x23, x23, #0x1",
"ubfx x23, x23, #0, #1",
@@ -2309,14 +2309,14 @@
"ExpectedInstructionCount": 19,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and x20, x5, #0x3f",
"and x20, x7, #0x3f",
"cbz x20, #+0x48",
"lsr x20, x4, x5",
"lsr x20, x4, x7",
"cset w21, lo",
"neg x22, x5",
"neg x22, x7",
"lsl x23, x4, x22",
"orr x20, x20, x23, lsl #1",
"sub x23, x5, #0x1 (1)",
"sub x23, x7, #0x1 (1)",
"lsr x23, x4, x23",
"eor x23, x23, #0x1",
"ubfx x23, x23, #0, #1",
@@ -2334,8 +2334,8 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"lsl w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x2c",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
@@ -2354,11 +2354,11 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"lsl w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x2c",
"ands w26, w20, w20",
"neg w0, w5",
"neg w0, w7",
"lsr w0, w4, w0",
"mvn x0, x0",
"eor w2, w4, w20",
@@ -2374,11 +2374,11 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl x20, x4, x5",
"and w0, w5, #0x3f",
"lsl x20, x4, x7",
"and w0, w7, #0x3f",
"cbz x0, #+0x2c",
"ands x26, x20, x20",
"neg x0, x5",
"neg x0, x7",
"lsr x0, x4, x0",
"mvn x0, x0",
"eor x2, x4, x20",
@@ -2395,12 +2395,12 @@
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, w5",
"and w0, w5, #0x1f",
"lsr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x30",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"eor w2, w20, w21",
@@ -2416,11 +2416,11 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"lsr w20, w4, w5",
"and w0, w5, #0x1f",
"lsr w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x2c",
"ands w26, w20, w20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w4, w0",
"mvn x0, x0",
"eor w2, w4, w20",
@@ -2436,11 +2436,11 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"lsr x20, x4, x5",
"and w0, w5, #0x3f",
"lsr x20, x4, x7",
"and w0, w7, #0x3f",
"cbz x0, #+0x2c",
"ands x26, x20, x20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr x0, x4, x0",
"mvn x0, x0",
"eor x2, x4, x20",
@@ -2457,12 +2457,12 @@
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"sxth x20, w4",
"asr w21, w20, w5",
"and w0, w5, #0x1f",
"asr w21, w20, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x24",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w20, w0",
"mvn x0, x0",
"mrs x1, nzcv",
@@ -2475,11 +2475,11 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"asr w20, w4, w5",
"and w0, w5, #0x1f",
"asr w20, w4, w7",
"and w0, w7, #0x1f",
"cbz w0, #+0x20",
"ands w26, w20, w20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr w0, w4, w0",
"mvn x0, x0",
"mrs x1, nzcv",
@@ -2492,11 +2492,11 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"asr x20, x4, x5",
"and w0, w5, #0x3f",
"asr x20, x4, x7",
"and w0, w7, #0x3f",
"cbz x0, #+0x20",
"ands x26, x20, x20",
"sub x0, x5, #0x1 (1)",
"sub x0, x7, #0x1 (1)",
"lsr x0, x4, x0",
"mvn x0, x0",
"mrs x1, nzcv",
@@ -2509,7 +2509,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf6 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0x1",
"and w26, w6, #0x1",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -2520,33 +2520,33 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"eor x7, x7, #0xff"
"eor x6, x6, #0xff"
]
},
"not bh": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"eor x7, x7, #0xff00"
"eor x6, x6, #0xff00"
]
},
"neg bl": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"mov x20, x7",
"cmp wzr, w6, lsl #24",
"neg w26, w6",
"mov x20, x6",
"bfxil x20, x26, #0, #8",
"mov x27, x7",
"mov x7, x20"
"mov x27, x6",
"mov x6, x20"
]
},
"mul bl": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf6 /4",
"ExpectedArm64ASM": [
"uxtb x20, w7",
"uxtb x20, w6",
"uxtb x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
@@ -2559,7 +2559,7 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf6 /5",
"ExpectedArm64ASM": [
"sxtb x20, w7",
"sxtb x20, w6",
"sxtb x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
@@ -2573,7 +2573,7 @@
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xf6 /6",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w20, w6",
"uxth w21, w4",
"uxth w0, w21",
"uxth w1, w20",
@@ -2590,7 +2590,7 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /7",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w20, w6",
"uxth w21, w4",
"sxth x21, w21",
"sxtb x20, w20",
@@ -2605,7 +2605,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0x1",
"and w26, w6, #0x1",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -2616,7 +2616,7 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w7, #0x1",
"ands w26, w6, #0x1",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -2626,7 +2626,7 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x7, #0x1",
"ands x26, x6, #0x1",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -2636,7 +2636,7 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x26, x7",
"mov x26, x6",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -2647,7 +2647,7 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands w26, w7, w7",
"ands w26, w6, w6",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -2657,7 +2657,7 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"ands x26, x7, x7",
"ands x26, x6, x6",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -2667,63 +2667,63 @@
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /1",
"ExpectedArm64ASM": [
"eor x7, x7, #0xffff"
"eor x6, x6, #0xffff"
]
},
"not ebx": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /1",
"ExpectedArm64ASM": [
"mvn w7, w7"
"mvn w6, w6"
]
},
"not rbx": {
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /1",
"ExpectedArm64ASM": [
"mvn x7, x7"
"mvn x6, x6"
]
},
"neg bx": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"mov x20, x7",
"cmp wzr, w6, lsl #16",
"neg w26, w6",
"mov x20, x6",
"bfxil x20, x26, #0, #16",
"mov x27, x7",
"mov x7, x20"
"mov x27, x6",
"mov x6, x20"
]
},
"neg ebx": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"negs w26, w7",
"mov x27, x7",
"mov x7, x26"
"negs w26, w6",
"mov x27, x6",
"mov x6, x26"
]
},
"neg rbx": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"negs x26, x7",
"mov x27, x7",
"mov x7, x26"
"negs x26, x6",
"mov x27, x6",
"mov x6, x26"
]
},
"mul bx": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"uxth x20, w7",
"uxth x20, w6",
"uxth x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"ubfx x20, x20, #16, #16",
"bfxil x6, x20, #0, #16",
"bfxil x5, x20, #0, #16",
"cmp x20, #0x0 (0)",
"ccmp xzr, #0, #nzcV, eq"
]
@@ -2732,12 +2732,12 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"mov w21, w4",
"mul x20, x20, x21",
"mov w4, w20",
"lsr x6, x20, #32",
"cmp x6, #0x0 (0)",
"lsr x5, x20, #32",
"cmp x5, #0x0 (0)",
"ccmp xzr, #0, #nzcV, eq"
]
},
@@ -2745,9 +2745,9 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"cmp x6, #0x0 (0)",
"mul x20, x6, x4",
"umulh x5, x6, x4",
"cmp x5, #0x0 (0)",
"ccmp xzr, #0, #nzcV, eq",
"mov x4, x20"
]
@@ -2756,12 +2756,12 @@
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"sxth x20, w7",
"sxth x20, w6",
"sxth x21, w4",
"mul x20, x20, x21",
"bfxil x4, x20, #0, #16",
"sbfx x21, x20, #16, #16",
"bfxil x6, x21, #0, #16",
"bfxil x5, x21, #0, #16",
"sbfx x20, x20, #15, #1",
"cmp x21, x20",
"ccmp xzr, #0, #nzcV, eq"
@@ -2771,11 +2771,11 @@
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"sxtw x20, w7",
"sxtw x20, w6",
"sxtw x21, w4",
"mul x20, x20, x21",
"mov w4, w20",
"lsr x6, x20, #32",
"lsr x5, x20, #32",
"asr x21, x20, #32",
"sxtw x20, w20",
"sbfx x20, x20, #31, #1",
@@ -2787,10 +2787,10 @@
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /5",
"ExpectedArm64ASM": [
"smulh x6, x7, x4",
"mul x4, x7, x4",
"smulh x5, x6, x4",
"mul x4, x6, x4",
"asr x20, x4, #63",
"cmp x6, x20",
"cmp x5, x20",
"ccmp xzr, #0, #nzcV, eq"
]
},
@@ -2798,9 +2798,9 @@
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xf7 /6",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"uxth w21, w4",
"uxth w22, w6",
"uxth w22, w5",
"uxth w0, w21",
"bfi w0, w22, #16, #16",
"udiv w23, w0, w20",
@@ -2809,16 +2809,16 @@
"udiv w1, w0, w20",
"msub w20, w1, w20, w0",
"bfxil x4, x23, #0, #16",
"bfxil x6, x20, #0, #16"
"bfxil x5, x20, #0, #16"
]
},
"div ebx": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xf7 /6",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"mov w21, w4",
"mov w22, w6",
"mov w22, w5",
"mov x0, x21",
"bfi x0, x22, #32, #32",
"udiv x23, x0, x20",
@@ -2827,36 +2827,36 @@
"bfi x0, x22, #32, #32",
"udiv x1, x0, x20",
"msub x20, x1, x20, x0",
"mov w6, w20"
"mov w5, w20"
]
},
"div rbx": {
"ExpectedInstructionCount": 24,
"Comment": "GROUP2 0xf7 /6",
"ExpectedArm64ASM": [
"cbz x6, #+0x28",
"mov x0, x6",
"cbz x5, #+0x28",
"mov x0, x5",
"mov x1, x4",
"mov x2, x7",
"mov x2, x6",
"ldr x3, [x28, #2736]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
"mov x20, x0",
"b #+0x8",
"udiv x20, x4, x7",
"cbz x6, #+0x28",
"mov x0, x6",
"udiv x20, x4, x6",
"cbz x5, #+0x28",
"mov x0, x5",
"mov x1, x4",
"mov x2, x7",
"mov x2, x6",
"ldr x3, [x28, #2752]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
"mov x6, x0",
"mov x5, x0",
"b #+0xc",
"udiv x0, x4, x7",
"msub x6, x0, x7, x4",
"udiv x0, x4, x6",
"msub x5, x0, x6, x4",
"mov x4, x20"
]
},
@@ -2864,9 +2864,9 @@
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xf7 /7",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"uxth w21, w4",
"uxth w22, w6",
"uxth w22, w5",
"uxth w0, w21",
"bfi w0, w22, #16, #16",
"sxth w1, w20",
@@ -2877,16 +2877,16 @@
"sdiv w2, w0, w1",
"msub w20, w2, w1, w0",
"bfxil x4, x23, #0, #16",
"bfxil x6, x20, #0, #16"
"bfxil x5, x20, #0, #16"
]
},
"idiv ebx": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xf7 /7",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"mov w21, w4",
"mov w22, w6",
"mov w22, w5",
"mov x0, x21",
"bfi x0, x22, #32, #32",
"sxtw x1, w20",
@@ -2897,7 +2897,7 @@
"sxtw x2, w20",
"sdiv x1, x0, x2",
"msub x20, x1, x2, x0",
"mov w6, w20"
"mov w5, w20"
]
},
"idiv rbx": {
@@ -2905,32 +2905,32 @@
"Comment": "GROUP2 0xf7 /7",
"ExpectedArm64ASM": [
"asr x0, x4, #63",
"eor x0, x0, x6",
"eor x0, x0, x5",
"cbz x0, #+0x28",
"mov x0, x6",
"mov x0, x5",
"mov x1, x4",
"mov x2, x7",
"mov x2, x6",
"ldr x3, [x28, #2744]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
"mov x20, x0",
"b #+0x8",
"sdiv x20, x4, x7",
"sdiv x20, x4, x6",
"asr x0, x4, #63",
"eor x0, x0, x6",
"eor x0, x0, x5",
"cbz x0, #+0x28",
"mov x0, x6",
"mov x0, x5",
"mov x1, x4",
"mov x2, x7",
"mov x2, x6",
"ldr x3, [x28, #2760]",
"str x30, [sp, #-16]!",
"blr x3",
"ldr x30, [sp], #16",
"mov x6, x0",
"mov x5, x0",
"b #+0xc",
"sdiv x0, x4, x7",
"msub x6, x0, x7, x4",
"sdiv x0, x4, x6",
"msub x5, x0, x6, x4",
"mov x4, x20"
]
},
unittests/InstructionCountCI/Primary_32Bit.json
+4 -4
View File
@@ -261,9 +261,9 @@
"ExpectedArm64ASM": [
"mov w20, w8",
"str w4, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
@@ -277,9 +277,9 @@
"ExpectedArm64ASM": [
"mov w20, w8",
"str w4, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
@@ -297,9 +297,9 @@
"ldr w9, [x20], #4",
"add x20, x20, #0x4 (4)",
"mov x8, x20",
"ldr w7, [x8], #4",
"ldr w6, [x8], #4",
"ldr w5, [x8], #4",
"ldr w7, [x8], #4",
"ldr w4, [x8], #4"
]
},
@@ -313,9 +313,9 @@
"ldr w9, [x20], #4",
"add x20, x20, #0x4 (4)",
"mov x8, x20",
"ldr w7, [x8], #4",
"ldr w6, [x8], #4",
"ldr w5, [x8], #4",
"ldr w7, [x8], #4",
"ldr w4, [x8], #4"
]
},
unittests/InstructionCountCI/SSE42_Strings.json
+20 -20
View File
@@ -42,11 +42,11 @@
],
"ExpectedArm64ASM": [
"mov x0, x4",
"mov x1, x6",
"mov x1, x5",
"mrs x2, nzcv",
"str w2, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -63,8 +63,8 @@
"blr x7",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -86,11 +86,11 @@
],
"ExpectedArm64ASM": [
"mov x0, x4",
"mov x1, x6",
"mov x1, x5",
"mrs x2, nzcv",
"str w2, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -107,8 +107,8 @@
"blr x7",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -124,7 +124,7 @@
"clz w23, w0",
"csinv w23, w23, wzr, ne",
"cmp x21, #0x0 (0)",
"csel x5, x22, x23, eq",
"csel x7, x22, x23, eq",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
@@ -138,8 +138,8 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -156,8 +156,8 @@
"blr x5",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -180,8 +180,8 @@
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -198,8 +198,8 @@
"blr x5",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -215,7 +215,7 @@
"clz w23, w0",
"csinv w23, w23, wzr, ne",
"cmp x21, #0x0 (0)",
"csel x5, x22, x23, eq",
"csel x7, x22, x23, eq",
"mov w26, #0x1",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
unittests/InstructionCountCI/Secondary.json
+182 -182
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+10 -14
View File
@@ -837,41 +837,37 @@
]
},
"cmpxchg8b [rbp]": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x20, x4",
"mov x21, x6",
"caspal w20, w21, w0, w1, [x9]",
"mov x21, x5",
"caspal w20, w21, w6, w7, [x9]",
"mrs x0, nzcv",
"cmp w20, w4",
"ccmp w21, w6, #nzcv, eq",
"ccmp w21, w5, #nzcv, eq",
"cset w1, eq",
"bfi w0, w1, #30, #1",
"msr nzcv, x0",
"csel x4, x20, x4, ne",
"csel x6, x21, x6, ne"
"csel x5, x21, x5, ne"
]
},
"cmpxchg16b [rbp]": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x20, x4",
"mov x21, x6",
"caspal x20, x21, x0, x1, [x9]",
"mov x21, x5",
"caspal x20, x21, x6, x7, [x9]",
"mrs x0, nzcv",
"cmp x20, x4",
"ccmp x21, x6, #nzcv, eq",
"ccmp x21, x5, #nzcv, eq",
"cset w1, eq",
"bfi w0, w1, #30, #1",
"msr nzcv, x0",
"csel x4, x20, x4, ne",
"csel x6, x21, x6, ne"
"csel x5, x21, x5, ne"
]
},
"rdrand ax": {
unittests/InstructionCountCI/SecondaryModRM.json
+8 -8
View File
@@ -26,8 +26,8 @@
"str x30, [x3]",
"mrs x3, nzcv",
"str w3, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -41,7 +41,7 @@
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x3], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
"mov w1, w5",
"mov w1, w7",
"ldr x0, [x28, #1368]",
"ldr x2, [x28, #1384]",
"blr x2",
@@ -52,8 +52,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -68,7 +68,7 @@
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov w4, w0",
"lsr x6, x0, #32"
"lsr x5, x0, #32"
]
},
"rdtscp": {
@@ -78,7 +78,7 @@
"dmb ld",
"mrs x20, S3_3_c14_c0_2",
"lsl w4, w20, #7",
"lsr x6, x20, #25",
"lsr x5, x20, #25",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"str x8, [x28, #312]",
@@ -95,7 +95,7 @@
"msr nzcv, x8",
"ldr x8, [x28, #312]",
"str xzr, [x28, #1312]",
"orr x5, x0, x1, lsl #12"
"orr x7, x0, x1, lsl #12"
]
},
"clzero rax": {
unittests/InstructionCountCI/Secondary_REP.json
+13 -13
View File
@@ -121,7 +121,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr s2, [x7]",
"ldr s2, [x6]",
"fcvtzs w4, s2"
]
},
@@ -136,7 +136,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0xf3 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x7]",
"ldr d2, [x6]",
"fcvtzs x4, s2"
]
},
@@ -152,7 +152,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr s2, [x7]",
"ldr s2, [x6]",
"frinti s0, s2",
"fcvtzs w4, s0"
]
@@ -169,7 +169,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf3 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x7]",
"ldr d2, [x6]",
"frinti s0, s2",
"fcvtzs x4, s0"
]
@@ -403,7 +403,7 @@
"ExpectedInstructionCount": 9,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w20, w6",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addp v0.8b, v0.8b, v0.8b",
@@ -418,7 +418,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov s0, w7",
"fmov s0, w6",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
@@ -431,7 +431,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"fmov d0, x6",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
@@ -444,7 +444,7 @@
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w20, w7",
"rbit w20, w6",
"orr w20, w20, #0x8000",
"clz w20, w20",
"bfxil x4, x20, #0, #16",
@@ -460,7 +460,7 @@
"ExpectedInstructionCount": 8,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit w4, w7",
"rbit w4, w6",
"clz w4, w4",
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
@@ -474,7 +474,7 @@
"ExpectedInstructionCount": 8,
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x4, x7",
"rbit x4, x6",
"clz x4, x4",
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
@@ -488,7 +488,7 @@
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"lsl w20, w7, #16",
"lsl w20, w6, #16",
"orr w20, w20, #0x8000",
"clz w20, w20",
"bfxil x4, x20, #0, #16",
@@ -504,7 +504,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz w4, w7",
"clz w4, w6",
"cmp w4, #0x0 (0)",
"eor x20, x4, #0x20",
"ubfx x20, x20, #5, #1",
@@ -517,7 +517,7 @@
"ExpectedInstructionCount": 7,
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"clz x4, x7",
"clz x4, x6",
"cmp x4, #0x0 (0)",
"eor x20, x4, #0x40",
"ubfx x20, x20, #6, #1",
unittests/InstructionCountCI/Secondary_REPNE.json
+4 -4
View File
@@ -106,7 +106,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x7]",
"ldr d2, [x6]",
"fcvtzs w4, d2"
]
},
@@ -121,7 +121,7 @@
"ExpectedInstructionCount": 2,
"Comment": "0xf2 0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x7]",
"ldr d2, [x6]",
"fcvtzs x4, d2"
]
},
@@ -137,7 +137,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x7]",
"ldr d2, [x6]",
"frinti d0, d2",
"fcvtzs x4, d0"
]
@@ -154,7 +154,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x7]",
"ldr d2, [x6]",
"frinti d0, d2",
"fcvtzs x4, d0"
]
unittests/InstructionCountCI/VEX_map2.json
+60 -60
View File
@@ -4900,7 +4900,7 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"bic w26, w7, w6",
"cmp w26, #0x0 (0)",
"mov x4, x26"
]
@@ -4911,7 +4911,7 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"bic x26, x7, x6",
"cmp x26, #0x0 (0)",
"mov x4, x26"
]
@@ -4923,10 +4923,10 @@
],
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"lsl w20, w20, w5",
"bic w20, w7, w20",
"tst x5, #0xe0",
"csel w4, w7, w20, ne",
"lsl w20, w20, w7",
"bic w20, w6, w20",
"tst x7, #0xe0",
"csel w4, w6, w20, ne",
"cset w20, eq",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
@@ -4941,10 +4941,10 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"lsl x20, x20, x5",
"bic x20, x7, x20",
"tst x5, #0xc0",
"csel x4, x7, x20, ne",
"lsl x20, x20, x7",
"bic x20, x6, x20",
"tst x7, #0xc0",
"csel x4, x6, x20, ne",
"cset w20, eq",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
@@ -4958,9 +4958,9 @@
"Map 2 0b10 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"cbz w5, #+0x2c",
"mov w0, w5",
"mov w2, w7",
"cbz w7, #+0x2c",
"mov w0, w7",
"mov w2, w6",
"mov w4, wzr",
"cbz w0, #+0x20",
"clz w1, w0",
@@ -4978,9 +4978,9 @@
"Map 2 0b10 0xf5 64-bit"
],
"ExpectedArm64ASM": [
"cbz x5, #+0x2c",
"mov x0, x5",
"mov x2, x7",
"cbz x7, #+0x2c",
"mov x0, x7",
"mov x2, x6",
"mov x4, xzr",
"cbz x0, #+0x20",
"clz x1, x0",
@@ -4998,10 +4998,10 @@
"Map 2 0b11 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x0, x6",
"mov x1, x7",
"mov w4, #0x0",
"cbz w5, #+0x2c",
"cbz w7, #+0x2c",
"neg w2, w1",
"and w2, w2, w1",
"sbfx w3, w0, #0, #1",
@@ -5020,10 +5020,10 @@
"Map 2 0b11 0xf5 64-bit"
],
"ExpectedArm64ASM": [
"mov x0, x7",
"mov x1, x5",
"mov x0, x6",
"mov x1, x7",
"mov x4, #0x0",
"cbz x5, #+0x2c",
"cbz x7, #+0x2c",
"neg x2, x1",
"and x2, x2, x1",
"sbfx x3, x0, #0, #1",
@@ -5042,9 +5042,9 @@
"Map 2 0b11 0xf6 32-bit"
],
"ExpectedArm64ASM": [
"mul w7, w5, w6",
"ubfx x0, x5, #0, #32",
"ubfx x1, x6, #0, #32",
"mul w6, w7, w5",
"ubfx x0, x7, #0, #32",
"ubfx x1, x5, #0, #32",
"mul x4, x0, x1",
"lsr x4, x4, #32"
]
@@ -5056,8 +5056,8 @@
"Map 2 0b11 0xf6 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x0, x7, #0, #32",
"ubfx x1, x6, #0, #32",
"ubfx x0, x6, #0, #32",
"ubfx x1, x5, #0, #32",
"mul x4, x0, x1",
"lsr x4, x4, #32"
]
@@ -5068,11 +5068,11 @@
"Map 2 0b11 0xf6 32-bit"
],
"ExpectedArm64ASM": [
"mov w20, w5",
"mov w20, w7",
"ldr w20, [x20]",
"mul w7, w20, w6",
"mul w6, w20, w5",
"ubfx x0, x20, #0, #32",
"ubfx x1, x6, #0, #32",
"ubfx x1, x5, #0, #32",
"mul x4, x0, x1",
"lsr x4, x4, #32"
]
@@ -5083,8 +5083,8 @@
"Map 2 0b11 0xf6 64-bit"
],
"ExpectedArm64ASM": [
"mul x7, x5, x6",
"umulh x4, x5, x6"
"mul x6, x7, x5",
"umulh x4, x7, x5"
]
},
"mulx rax, rax, rbx": {
@@ -5094,7 +5094,7 @@
"Map 2 0b11 0xf6 64-bit"
],
"ExpectedArm64ASM": [
"umulh x4, x7, x6"
"umulh x4, x6, x5"
]
},
"mulx rax, rbx, [rcx]": {
@@ -5103,9 +5103,9 @@
"Map 2 0b11 0xf6 64-bit"
],
"ExpectedArm64ASM": [
"ldr x20, [x5]",
"mul x7, x20, x6",
"umulh x4, x20, x6"
"ldr x20, [x7]",
"mul x6, x20, x5",
"umulh x4, x20, x5"
]
},
"bextr eax, ebx, ecx": {
@@ -5114,12 +5114,12 @@
"Map 2 0b00 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"uxtb w20, w5",
"lsr w21, w7, w20",
"uxtb w20, w7",
"lsr w21, w6, w20",
"mov w22, #0x0",
"cmp w20, #0x1f (31)",
"csel w20, w21, w22, ls",
"ubfx w21, w5, #8, #8",
"ubfx w21, w7, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl w22, w22, w21",
"bic w22, w20, w22",
@@ -5134,12 +5134,12 @@
"Map 2 0b00 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"uxtb x20, w5",
"lsr x21, x7, x20",
"uxtb x20, w7",
"lsr x21, x6, x20",
"mov w22, #0x0",
"cmp x20, #0x3f (63)",
"csel x20, x21, x22, ls",
"ubfx x21, x5, #8, #8",
"ubfx x21, x7, #8, #8",
"mov x22, #0xffffffffffffffff",
"lsl x22, x22, x21",
"bic x22, x20, x22",
@@ -5154,7 +5154,7 @@
"Map 2 0b01 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"lsl w4, w7, w5"
"lsl w4, w6, w7"
]
},
"shlx eax, [ebx], ecx": {
@@ -5163,9 +5163,9 @@
"Map 2 0b01 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"ldr w20, [x20]",
"lsl w4, w20, w5"
"lsl w4, w20, w7"
]
},
"shlx rax, rbx, rcx": {
@@ -5174,7 +5174,7 @@
"Map 2 0b01 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"lsl x4, x7, x5"
"lsl x4, x6, x7"
]
},
"shlx rax, [rbx], rcx": {
@@ -5183,8 +5183,8 @@
"Map 2 0b01 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"ldr x20, [x7]",
"lsl x4, x20, x5"
"ldr x20, [x6]",
"lsl x4, x20, x7"
]
},
"sarx eax, ebx, ecx": {
@@ -5193,7 +5193,7 @@
"Map 2 0b10 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"asr w4, w7, w5"
"asr w4, w6, w7"
]
},
"sarx eax, [ebx], ecx": {
@@ -5202,9 +5202,9 @@
"Map 2 0b10 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"ldr w20, [x20]",
"asr w4, w20, w5"
"asr w4, w20, w7"
]
},
"sarx rax, rbx, rcx": {
@@ -5213,7 +5213,7 @@
"Map 2 0b10 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"asr x4, x7, x5"
"asr x4, x6, x7"
]
},
"sarx rax, [rbx], rcx": {
@@ -5222,8 +5222,8 @@
"Map 2 0b10 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"ldr x20, [x7]",
"asr x4, x20, x5"
"ldr x20, [x6]",
"asr x4, x20, x7"
]
},
"shrx eax, ebx, ecx": {
@@ -5232,7 +5232,7 @@
"Map 2 0b11 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"lsr w4, w7, w5"
"lsr w4, w6, w7"
]
},
"shrx eax, [ebx], ecx": {
@@ -5241,9 +5241,9 @@
"Map 2 0b11 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w20, w6",
"ldr w20, [x20]",
"lsr w4, w20, w5"
"lsr w4, w20, w7"
]
},
"shrx rax, rbx, rcx": {
@@ -5252,7 +5252,7 @@
"Map 2 0b11 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"lsr x4, x7, x5"
"lsr x4, x6, x7"
]
},
"shrx rax, [rbx], rcx": {
@@ -5261,8 +5261,8 @@
"Map 2 0b11 0xf7 64-bit"
],
"ExpectedArm64ASM": [
"ldr x20, [x7]",
"lsr x4, x20, x5"
"ldr x20, [x6]",
"lsr x4, x20, x7"
]
}
}
unittests/InstructionCountCI/VEX_map2_svebitperm.json
+8 -8
View File
@@ -19,8 +19,8 @@
"Map 2 0b10 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"fmov s0, w7",
"fmov s1, w5",
"fmov s0, w6",
"fmov s1, w7",
"bext z0.s, z0.s, z1.s",
"mov w4, v0.s[0]"
]
@@ -31,8 +31,8 @@
"Map 2 0b10 0xf5 64-bit"
],
"ExpectedArm64ASM": [
"fmov d0, x7",
"fmov d1, x5",
"fmov d0, x6",
"fmov d1, x7",
"bext z0.d, z0.d, z1.d",
"mov x4, v0.d[0]"
]
@@ -43,8 +43,8 @@
"Map 2 0b11 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"fmov s0, w7",
"fmov s1, w5",
"fmov s0, w6",
"fmov s1, w7",
"bdep z0.s, z0.s, z1.s",
"mov w4, v0.s[0]"
]
@@ -55,8 +55,8 @@
"Map 2 0b11 0xf5 64-bit"
],
"ExpectedArm64ASM": [
"fmov d0, x7",
"fmov d1, x5",
"fmov d0, x6",
"fmov d1, x7",
"bdep z0.d, z0.d, z1.d",
"mov x4, v0.d[0]"
]
unittests/InstructionCountCI/VEX_map3.json
+6 -6
View File
@@ -5401,7 +5401,7 @@
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"mov w4, w7"
"mov w4, w6"
]
},
"rorx eax, eax, 0": {
@@ -5419,7 +5419,7 @@
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"ror w4, w7, #31"
"ror w4, w6, #31"
]
},
"rorx eax, ebx, 32": {
@@ -5428,7 +5428,7 @@
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"mov w4, w7"
"mov w4, w6"
]
},
"rorx eax, eax, 32": {
@@ -5446,7 +5446,7 @@
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": [
"mov x4, x7"
"mov x4, x6"
]
},
"rorx rax, rax, 0": {
@@ -5462,7 +5462,7 @@
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": [
"ror x4, x7, #63"
"ror x4, x6, #63"
]
},
"rorx rax, rbx, 64": {
@@ -5471,7 +5471,7 @@
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": [
"mov x4, x7"
"mov x4, x6"
]
},
"rorx rax, rax, 64": {
unittests/InstructionCountCI/VEX_map_group.json
+16 -16
View File
@@ -613,9 +613,9 @@
"Map group 17 0b001 32-bit"
],
"ExpectedArm64ASM": [
"sub w20, w7, #0x1 (1)",
"and w4, w20, w7",
"cmp x7, #0x0 (0)",
"sub w20, w6, #0x1 (1)",
"and w4, w20, w6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
@@ -629,9 +629,9 @@
"Map group 17 0b001 64-bit"
],
"ExpectedArm64ASM": [
"sub x20, x7, #0x1 (1)",
"and x4, x20, x7",
"cmp x7, #0x0 (0)",
"sub x20, x6, #0x1 (1)",
"and x4, x20, x6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
@@ -645,9 +645,9 @@
"Map group 17 0b010 32-bit"
],
"ExpectedArm64ASM": [
"sub w20, w7, #0x1 (1)",
"eor w4, w20, w7",
"cmp x7, #0x0 (0)",
"sub w20, w6, #0x1 (1)",
"eor w4, w20, w6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp w4, #0x0 (0)",
"mrs x21, nzcv",
@@ -661,9 +661,9 @@
"Map group 17 0b010 64-bit"
],
"ExpectedArm64ASM": [
"sub x20, x7, #0x1 (1)",
"eor x4, x20, x7",
"cmp x7, #0x0 (0)",
"sub x20, x6, #0x1 (1)",
"eor x4, x20, x6",
"cmp x6, #0x0 (0)",
"cset x20, ne",
"cmp x4, #0x0 (0)",
"mrs x21, nzcv",
@@ -677,8 +677,8 @@
"Map group 17 0b011 32-bit"
],
"ExpectedArm64ASM": [
"neg w20, w7",
"and w4, w7, w20",
"neg w20, w6",
"and w4, w6, w20",
"cmp w4, #0x0 (0)",
"cset w20, eq",
"mrs x21, nzcv",
@@ -692,8 +692,8 @@
"Map group 17 0b011 64-bit"
],
"ExpectedArm64ASM": [
"neg x20, x7",
"and x4, x7, x20",
"neg x20, x6",
"and x4, x6, x20",
"cmp x4, #0x0 (0)",
"cset w20, eq",
"mrs x21, nzcv",
unittests/InstructionCountCI/x87.json
+1236 -1236
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64.json
+144 -144
View File
@@ -2279,8 +2279,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2317,8 +2317,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2349,8 +2349,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2386,8 +2386,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2415,8 +2415,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2453,8 +2453,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2498,8 +2498,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2535,8 +2535,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2601,8 +2601,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2638,8 +2638,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2695,8 +2695,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2732,8 +2732,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2772,8 +2772,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2809,8 +2809,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2852,8 +2852,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2890,8 +2890,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2903,8 +2903,8 @@
"mov v3.8b, v0.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -2941,8 +2941,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -2998,8 +2998,8 @@
"mov v1.8b, v2.8b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -3035,8 +3035,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -3061,8 +3061,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -3099,8 +3099,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -3126,8 +3126,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"stp x8, x9, [x28, #312]",
"stp x10, x11, [x28, #328]",
"stp x12, x13, [x28, #344]",
@@ -3164,8 +3164,8 @@
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldp x8, x9, [x28, #312]",
"ldp x10, x11, [x28, #328]",
"ldp x12, x13, [x28, #344]",
@@ -4137,8 +4137,8 @@
"ldr q2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -4153,8 +4153,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -4185,8 +4185,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -4200,8 +4200,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6479,8 +6479,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6495,8 +6495,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6511,8 +6511,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6527,8 +6527,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6543,8 +6543,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6559,8 +6559,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6575,8 +6575,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6591,8 +6591,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6607,8 +6607,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6623,8 +6623,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6639,8 +6639,8 @@
"and v3.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6655,8 +6655,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6671,8 +6671,8 @@
"and v2.16b, v3.16b, v2.16b",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6687,8 +6687,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6704,8 +6704,8 @@
"mov v2.h[4], v3.h[0]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6720,8 +6720,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6806,8 +6806,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6821,8 +6821,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6838,8 +6838,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6853,8 +6853,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6870,8 +6870,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6885,8 +6885,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6902,8 +6902,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6917,8 +6917,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6934,8 +6934,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6949,8 +6949,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6966,8 +6966,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -6981,8 +6981,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -6998,8 +6998,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -7013,8 +7013,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -7030,8 +7030,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -7045,8 +7045,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9566,8 +9566,8 @@
"ldr q2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9582,8 +9582,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9594,8 +9594,8 @@
"mov v2.h[4], w1",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9610,8 +9610,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9642,8 +9642,8 @@
"ldr d2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9657,8 +9657,8 @@
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -9669,8 +9669,8 @@
"mov v2.h[4], w1",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"stp x4, x7, [x28, #280]",
"stp x5, x6, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
@@ -9685,8 +9685,8 @@
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldp x4, x7, [x28, #280]",
"ldp x5, x6, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
@@ -10361,15 +10361,15 @@
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str s2, [x6]",
"str s2, [x5]",
"ldr s2, [x4, #4]",
"add x20, x6, #0x4 (4)",
"add x20, x5, #0x4 (4)",
"str s2, [x20]",
"ldr s2, [x4, #8]",
"add x20, x6, #0x8 (8)",
"add x20, x5, #0x8 (8)",
"str s2, [x20]",
"ldr s2, [x4, #12]",
"add x20, x6, #0xc (12)",
"add x20, x5, #0xc (12)",
"str s2, [x20]",
"ldrb w20, [x28, #1019]",
"add w20, w20, #0x7 (7)",
@@ -10395,15 +10395,15 @@
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str d2, [x6]",
"str d2, [x5]",
"ldr d2, [x4, #8]",
"add x20, x6, #0x8 (8)",
"add x20, x5, #0x8 (8)",
"str d2, [x20]",
"ldr d2, [x4, #16]",
"add x20, x6, #0x10 (16)",
"add x20, x5, #0x10 (16)",
"str d2, [x20]",
"ldr d2, [x4, #32]",
"add x20, x6, #0x20 (32)",
"add x20, x5, #0x20 (32)",
"str d2, [x20]",
"ldrb w20, [x28, #1019]",
"add w20, w20, #0x7 (7)",