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Merge pull request #74 from Sonicadvance1/mmx_insts

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Implements 80 new MMX instructions
This commit is contained in:
Ryan Houdek authored and GitHub committed 2020-04-05 00:31:31 -07:00
2 parents 3e7fe47f23 fd4fb37056
commit 8e369da1e9
81 files changed
+3036 -117
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External/FEXCore/Source/Interface/Core/Frontend.cpp
Vendored
+8 -8
View File
@@ -80,14 +80,14 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
FEXCore::X86State::REG_MM_5,
FEXCore::X86State::REG_MM_6,
FEXCore::X86State::REG_MM_7,
~0ULL,
~0ULL,
~0ULL,
~0ULL,
~0ULL,
~0ULL,
~0ULL,
~0ULL
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID,
FEXCore::X86State::REG_INVALID
};
const std::array<uint64_t, 16> *GPRs = &GPRIndexes;
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp
Vendored
+7
View File
@@ -1936,6 +1936,13 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
break;
}
case IR::OP_VMOV: {
auto Op = IROp->C<IR::IROp_VMov>();
__uint128_t Src = *GetSrc<__uint128_t*>(Op->Header.Args[0]);
memcpy(GDP, &Src, Op->RegisterSize);
break;
}
case IR::OP_VOR: {
auto Op = IROp->C<IR::IROp_VOr>();
__uint128_t Src1 = *GetSrc<__uint128_t*>(Op->Header.Args[0]);
External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
Vendored
+39
View File
@@ -331,6 +331,12 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
IR::OrderedNode *BlockNode = HeaderOp->Blocks.GetNode(ListBegin);
auto GetArgSize = [&](FEXCore::IR::OrderedNodeWrapper ArgWrapper) {
FEXCore::IR::OrderedNode *Arg = ArgWrapper.GetNode(ListBegin);
FEXCore::IR::IROp_Header *IROp = Arg->Op(DataBegin);
return IROp->Size * std::max((uint8_t)1, IROp->Elements);
};
while (1) {
using namespace FEXCore::IR;
auto BlockIROp = BlockNode->Op(DataBegin)->CW<FEXCore::IR::IROp_CodeBlock>();
@@ -2038,6 +2044,39 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
}
break;
}
case IR::OP_VMOV: {
auto Op = IROp->C<IR::IROp_VMov>();
switch (GetArgSize(Op->Header.Args[0])) {
case 1: {
eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
mov(VTMP1.V16B(), 0, GetSrc(Op->Header.Args[0].ID()).V16B(), 0);
mov(GetDst(Node), VTMP1);
break;
}
case 2: {
eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
mov(VTMP1.V8H(), 0, GetSrc(Op->Header.Args[0].ID()).V8H(), 0);
mov(GetDst(Node), VTMP1);
break;
}
case 4: {
eor(VTMP1.V16B(), VTMP1.V16B(), VTMP1.V16B());
mov(VTMP1.V4S(), 0, GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
mov(GetDst(Node), VTMP1);
break;
}
case 8: {
mov(GetDst(Node).V8B(), GetSrc(Op->Header.Args[0].ID()).V8B());
break;
}
case 16: {
mov(GetDst(Node).V16B(), GetSrc(Op->Header.Args[0].ID()).V16B());
break;
}
default: LogMan::Msg::A("Unknown Element Size: %d", GetArgSize(Op->Header.Args[0])); break;
}
break;
}
case IR::OP_VINSELEMENT: {
auto Op = IROp->C<IR::IROp_VInsElement>();
mov(VTMP1, GetSrc(Op->Header.Args[0].ID()));
External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
Vendored
+44
View File
@@ -314,6 +314,12 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
L(IsTarget->second);
}
auto GetArgSize = [&](OrderedNodeWrapper ArgWrapper) {
OrderedNode *Arg = ArgWrapper.GetNode(ListBegin);
FEXCore::IR::IROp_Header *IROp = Arg->Op(DataBegin);
return IROp->Size * std::max((uint8_t)1, IROp->Elements);
};
while (1) {
OrderedNodeWrapper *WrapperOp = CodeBegin();
OrderedNode *RealNode = WrapperOp->GetNode(ListBegin);
@@ -2343,6 +2349,44 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
}
break;
}
case IR::OP_VMOV: {
auto Op = IROp->C<IR::IROp_VMov>();
switch (GetArgSize(Op->Header.Args[0])) {
case 1: {
vpxor(xmm15, xmm15, xmm15);
pextrb(eax, GetSrc(Op->Header.Args[0].ID()), 0);
pinsrb(xmm15, eax, 0);
movapd(GetDst(Node), xmm15);
break;
}
case 2: {
vpxor(xmm15, xmm15, xmm15);
pextrw(eax, GetSrc(Op->Header.Args[0].ID()), 0);
pinsrw(xmm15, eax, 0);
movapd(GetDst(Node), xmm15);
break;
}
case 4: {
vpxor(xmm15, xmm15, xmm15);
pextrd(eax, GetSrc(Op->Header.Args[0].ID()), 0);
pinsrd(xmm15, eax, 0);
movapd(GetDst(Node), xmm15);
break;
}
case 8: {
movq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
break;
}
case 16: {
movaps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
break;
}
default: LogMan::Msg::A("Unknown Element Size: %d", GetArgSize(Op->Header.Args[0])); break;
}
break;
}
case IR::OP_VAND: {
auto Op = IROp->C<IR::IROp_VAnd>();
vpand(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
External/FEXCore/Source/Interface/Core/LLVMJIT/LLVMCore.cpp
Vendored
+24
View File
@@ -1402,6 +1402,12 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
FEXCore::IR::IROp_Header *IROp = RealNode->Op(DataBegin);
uint8_t OpSize = IROp->Size;
auto GetArgSize = [&](FEXCore::IR::OrderedNodeWrapper ArgWrapper) {
FEXCore::IR::OrderedNode *Arg = ArgWrapper.GetNode(ListBegin);
FEXCore::IR::IROp_Header *IROp = Arg->Op(DataBegin);
return IROp->Size * std::max((uint8_t)1, IROp->Elements);
};
switch (IROp->Op) {
case IR::OP_ENDBLOCK: {
auto Op = IROp->C<IR::IROp_EndBlock>();
@@ -2300,6 +2306,24 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
SetDest(*WrapperOp, Result);
break;
}
case IR::OP_VMOV: {
auto Op = IROp->C<IR::IROp_VMov>();
auto Src = GetSrc(Op->Header.Args[0]);
uint8_t ArgSize = GetArgSize(Op->Header.Args[0]);
// Cast to the type we want
Src = CastScalarToType(Src, true, ArgSize, ArgSize);
if (Op->RegisterSize != ArgSize) {
auto Result = JITState.IRBuilder->CreateZExt(Src, Type::getIntNTy(*Con, Op->RegisterSize * 8));
SetDest(*WrapperOp, Result);
}
else {
SetDest(*WrapperOp, Src);
}
break;
}
case IR::OP_VBITCAST: {
auto Op = IROp->C<IR::IROp_VBitcast>();
auto Src = GetSrc(Op->Header.Args[0]);
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+269 -24
View File
@@ -2689,6 +2689,15 @@ void OpDispatchBuilder::PMINSWOp(OpcodeArgs) {
StoreResult(FPRClass, Op, ALUOp, -1);
}
void OpDispatchBuilder::PMAXSWOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
auto ALUOp = _VSMax(Size, 2, Dest, Src);
StoreResult(FPRClass, Op, ALUOp, -1);
}
template<FEXCore::IR::IROps IROp, size_t ElementSize>
void OpDispatchBuilder::VectorALUOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
@@ -2799,7 +2808,7 @@ void OpDispatchBuilder::PUNPCKHOp(OpcodeArgs) {
StoreResult(FPRClass, Op, ALUOp, -1);
}
template<size_t ElementSize, bool Low>
template<size_t ElementSize, bool HalfSize, bool Low>
void OpDispatchBuilder::PSHUFDOp(OpcodeArgs) {
LogMan::Throw::A(ElementSize != 0, "What. No element size?");
auto Size = GetSrcSize(Op);
@@ -2812,7 +2821,7 @@ void OpDispatchBuilder::PSHUFDOp(OpcodeArgs) {
// It only ever operates on half the register
// Then there is a high and low variant of the instruction to determine where the destination goes
// and where the source comes from
if (ElementSize == 2) {
if (HalfSize) {
NumElements /= 2;
}
@@ -3178,7 +3187,10 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(FEXCore::IR::RegisterClass
Src = _Constant(Operand.TypeLiteral.Size * 8, Operand.TypeLiteral.Literal);
}
else if (Operand.TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_GPR) {
if (Operand.TypeGPR.GPR >= FEXCore::X86State::REG_XMM_0) {
if (Operand.TypeGPR.GPR >= FEXCore::X86State::REG_MM_0) {
Src = _LoadContext(OpSize, offsetof(FEXCore::Core::CPUState, mm[Operand.TypeGPR.GPR - FEXCore::X86State::REG_MM_0]), FPRClass);
}
else if (Operand.TypeGPR.GPR >= FEXCore::X86State::REG_XMM_0) {
Src = _LoadContext(OpSize, offsetof(FEXCore::Core::CPUState, xmm[Operand.TypeGPR.GPR - FEXCore::X86State::REG_XMM_0][Operand.TypeGPR.HighBits ? 1 : 0]), FPRClass);
}
else {
@@ -3283,7 +3295,10 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
MemStore = true; // Literals are ONLY hardcoded memory destinations
}
else if (Operand.TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_GPR) {
if (Operand.TypeGPR.GPR >= FEXCore::X86State::REG_XMM_0) {
if (Operand.TypeGPR.GPR >= FEXCore::X86State::REG_MM_0) {
_StoreContext(Src, OpSize, offsetof(FEXCore::Core::CPUState, mm[Operand.TypeGPR.GPR - FEXCore::X86State::REG_MM_0]), Class);
}
else if (Operand.TypeGPR.GPR >= FEXCore::X86State::REG_XMM_0) {
_StoreContext(Src, OpSize, offsetof(FEXCore::Core::CPUState, xmm[Operand.TypeGPR.GPR - FEXCore::X86State::REG_XMM_0][Operand.TypeGPR.HighBits ? 1 : 0]), Class);
}
else {
@@ -4660,6 +4675,7 @@ void OpDispatchBuilder::MOVBetweenGPR_FPR(OpcodeArgs) {
OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
// When destination is XMM then it is zext to 128bit
uint64_t SrcSize = GetSrcSize(Op) * 8;
while (SrcSize != 128) {
Src = _Zext(SrcSize, Src);
SrcSize *= 2;
@@ -5031,6 +5047,19 @@ void OpDispatchBuilder::PACKUSOp(OpcodeArgs) {
StoreResult(FPRClass, Op, Res, -1);
}
template<size_t ElementSize>
void OpDispatchBuilder::PACKSSOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Res = _VSQXTN(Size, ElementSize, Dest);
Res = _VSQXTN2(Size, ElementSize, Res, Src);
StoreResult(FPRClass, Op, Res, -1);
}
template<size_t ElementSize, bool Signed>
void OpDispatchBuilder::PMULLOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
@@ -5038,29 +5067,161 @@ void OpDispatchBuilder::PMULLOp(OpcodeArgs) {
OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode* Srcs1[2]{};
OrderedNode* Srcs2[2]{};
Srcs1[0] = _VExtr(Size, ElementSize, Src1, Src1, 0);
Srcs1[1] = _VExtr(Size, ElementSize, Src1, Src1, 2);
Srcs2[0] = _VExtr(Size, ElementSize, Src2, Src2, 0);
Srcs2[1] = _VExtr(Size, ElementSize, Src2, Src2, 2);
Src1 = _VInsElement(Size, ElementSize, 1, 0, Srcs1[0], Srcs1[1]);
Src2 = _VInsElement(Size, ElementSize, 1, 0, Srcs2[0], Srcs2[1]);
OrderedNode *Res{};
if (Signed) {
Res = _VSMull(Size, ElementSize, Src1, Src2);
if (Size == 8) {
if (Signed) {
Res = _VSMull(16, ElementSize, Src1, Src2);
}
else {
Res = _VUMull(16, ElementSize, Src1, Src2);
}
}
else {
Res = _VUMull(Size, ElementSize, Src1, Src2);
OrderedNode* Srcs1[2]{};
OrderedNode* Srcs2[2]{};
Srcs1[0] = _VExtr(Size, ElementSize, Src1, Src1, 0);
Srcs1[1] = _VExtr(Size, ElementSize, Src1, Src1, 2);
Srcs2[0] = _VExtr(Size, ElementSize, Src2, Src2, 0);
Srcs2[1] = _VExtr(Size, ElementSize, Src2, Src2, 2);
Src1 = _VInsElement(Size, ElementSize, 1, 0, Srcs1[0], Srcs1[1]);
Src2 = _VInsElement(Size, ElementSize, 1, 0, Srcs2[0], Srcs2[1]);
if (Signed) {
Res = _VSMull(Size, ElementSize, Src1, Src2);
}
else {
Res = _VUMull(Size, ElementSize, Src1, Src2);
}
}
StoreResult(FPRClass, Op, Res, -1);
}
template<bool ToXMM>
void OpDispatchBuilder::MOVQ2DQ(OpcodeArgs) {
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
// This instruction is a bit special in that if the source is MMX then it zexts to 128bit
if (ToXMM) {
Src = _VMov(Src, 16);
_StoreContext(FPRClass, 16, offsetof(FEXCore::Core::CPUState, xmm[Op->Dest.TypeGPR.GPR - FEXCore::X86State::REG_XMM_0][0]), Src);
}
else {
// This is simple, just store the result
StoreResult(FPRClass, Op, Src, -1);
}
}
template<size_t ElementSize, bool Signed>
void OpDispatchBuilder::PADDSOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Res{};
if (Signed)
Res = _VSQAdd(Size, ElementSize, Dest, Src);
else
Res = _VUQAdd(Size, ElementSize, Dest, Src);
StoreResult(FPRClass, Op, Res, -1);
}
template<size_t ElementSize, bool Signed>
void OpDispatchBuilder::PSUBSOp(OpcodeArgs) {
auto Size = GetSrcSize(Op);
OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Res{};
if (Signed)
Res = _VSQSub(Size, ElementSize, Dest, Src);
else
Res = _VUQSub(Size, ElementSize, Dest, Src);
StoreResult(FPRClass, Op, Res, -1);
}
void OpDispatchBuilder::PMADDWD(OpcodeArgs) {
// This is a pretty curious operation
// Does two MADD operations across 4 16bit signed integers and accumulates to 32bit integers in the destination
//
// x86 PMADDWD: xmm1, xmm2
// xmm1[31:0] = (xmm1[15:0] * xmm2[15:0]) + (xmm1[31:16] * xmm2[31:16])
// xmm1[63:32] = (xmm1[47:32] * xmm2[47:32]) + (xmm1[63:48] * xmm2[63:48])
// etc.. for larger registers
auto Size = GetSrcSize(Op);
OrderedNode *Src1 = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
if (Size == 8) {
Size <<= 1;
Src1 = _VBitcast(Size, 2, Src1);
Src2 = _VBitcast(Size, 2, Src2);
}
auto Src1_L = _VSXTL(Size, 2, Src1); // [15:0 ], [31:16], [32:47 ], [63:48 ]
auto Src1_H = _VSXTL2(Size, 2, Src1); // [79:64], [95:80], [111:96], [127:112]
auto Src2_L = _VSXTL(Size, 2, Src2); // [15:0 ], [31:16], [32:47 ], [63:48 ]
auto Src2_H = _VSXTL2(Size, 2, Src2); // [79:64], [95:80], [111:96], [127:112]
auto Res_L = _VSMul(Size, 4, Src1_L, Src2_L); // [15:0 ], [31:16], [32:47 ], [63:48 ] : Original elements
auto Res_H = _VSMul(Size, 4, Src1_H, Src2_H); // [79:64], [95:80], [111:96], [127:112] : Original elements
// [15:0 ] + [31:16], [32:47 ] + [63:48 ], [79:64] + [95:80], [111:96] + [127:112]
auto Res = _VAddP(Size, 4, Res_L, Res_H);
StoreResult(FPRClass, Op, Res, -1);
}
template<bool Signed>
void OpDispatchBuilder::PMULHW(OpcodeArgs) {
auto Size = GetSrcSize(Op);
OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Res{};
if (Size == 8) {
Dest = _VBitcast(Size * 2, 2, Dest);
Src = _VBitcast(Size * 2, 2, Src);
// Implementation is more efficient for 8byte registers
if (Signed)
Res = _VSMull(Size * 2, 2, Dest, Src);
else
Res = _VUMull(Size * 2, 2, Dest, Src);
Res = _VUShrNI(Size * 2, 4, Res, 16);
}
else {
// 128bit is less efficient
OrderedNode *ResultLow;
OrderedNode *ResultHigh;
if (Signed) {
ResultLow = _VSMull(Size, 2, Dest, Src);
ResultHigh = _VSMull2(Size, 2, Dest, Src);
}
else {
ResultLow = _VUMull(Size, 2, Dest, Src);
ResultHigh = _VUMull2(Size, 2, Dest, Src);
}
// Combine the results
Res = _VUShrNI(Size, 4, ResultLow, 16);
Res = _VUShrNI2(Size, 4, Res, ResultHigh, 16);
}
StoreResult(FPRClass, Op, Res, -1);
}
void OpDispatchBuilder::UnimplementedOp(OpcodeArgs) {
// We don't actually support this instruction
// Multiblock may hit it though
@@ -5214,6 +5375,7 @@ void InstallOpcodeHandlers() {
{0x05, 1, &OpDispatchBuilder::SyscallOp},
{0x0B, 1, &OpDispatchBuilder::INTOp},
{0x0D, 1, nullptr}, // GROUP P
{0x0E, 1, &OpDispatchBuilder::NOPOp},
{0x18, 1, nullptr}, // GROUP 16
{0x19, 7, &OpDispatchBuilder::NOPOp}, // NOP with ModRM
@@ -5221,8 +5383,10 @@ void InstallOpcodeHandlers() {
{0x31, 1, &OpDispatchBuilder::RDTSCOp},
{0x40, 16, &OpDispatchBuilder::CMOVOp},
{0x6E, 1, &OpDispatchBuilder::UnhandledOp}, // MOVD
{0x7E, 1, &OpDispatchBuilder::UnhandledOp}, // MOVD
{0x6E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR},
{0x6F, 1, &OpDispatchBuilder::MOVUPSOp},
{0x7E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR},
{0x7F, 1, &OpDispatchBuilder::MOVUPSOp},
{0x80, 16, &OpDispatchBuilder::CondJUMPOp},
{0x90, 16, &OpDispatchBuilder::SETccOp},
{0xA2, 1, &OpDispatchBuilder::CPUIDOp},
@@ -5241,6 +5405,9 @@ void InstallOpcodeHandlers() {
{0xBD, 1, &OpDispatchBuilder::BSROp}, // BSF
{0xBE, 2, &OpDispatchBuilder::MOVSXOp},
{0xC0, 2, &OpDispatchBuilder::XADDOp},
{0xC3, 1, &OpDispatchBuilder::MOVGPROp<0>},
{0xC4, 1, &OpDispatchBuilder::PINSROp<2>},
{0xC5, 1, &OpDispatchBuilder::PExtrOp<2>},
{0xC8, 8, &OpDispatchBuilder::BSWAPOp},
// SSE
@@ -5251,6 +5418,7 @@ void InstallOpcodeHandlers() {
{0x16, 1, &OpDispatchBuilder::MOVLHPSOp},
{0x17, 1, &OpDispatchBuilder::MOVUPSOp},
{0x28, 2, &OpDispatchBuilder::MOVUPSOp},
{0x2B, 1, &OpDispatchBuilder::MOVAPSOp},
{0x2E, 2, &OpDispatchBuilder::UCOMISxOp<4>},
{0x50, 1, &OpDispatchBuilder::MOVMSKOp<4>},
{0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 4, false>},
@@ -5267,10 +5435,28 @@ void InstallOpcodeHandlers() {
{0x5D, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFMIN, 4>},
{0x5E, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFDIV, 4>},
{0x5F, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFMAX, 4>},
{0x60, 1, &OpDispatchBuilder::PUNPCKLOp<1>},
{0x61, 1, &OpDispatchBuilder::PUNPCKLOp<2>},
{0x62, 1, &OpDispatchBuilder::PUNPCKLOp<4>},
{0x63, 1, &OpDispatchBuilder::PACKSSOp<2>},
{0x64, 1, &OpDispatchBuilder::PCMPGTOp<1>},
{0x65, 1, &OpDispatchBuilder::PCMPGTOp<2>},
{0x66, 1, &OpDispatchBuilder::PCMPGTOp<4>},
{0x67, 1, &OpDispatchBuilder::PACKUSOp<2>},
{0x68, 1, &OpDispatchBuilder::PUNPCKHOp<1>},
{0x69, 1, &OpDispatchBuilder::PUNPCKHOp<2>},
{0x6A, 1, &OpDispatchBuilder::PUNPCKHOp<4>},
{0x6B, 1, &OpDispatchBuilder::PACKSSOp<4>},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, false, true>},
{0x71, 1, nullptr}, // GROUP 12
{0x72, 1, nullptr}, // GROUP 13
{0x73, 1, nullptr}, // GROUP 14
{0x74, 1, &OpDispatchBuilder::PCMPEQOp<1>},
{0x75, 1, &OpDispatchBuilder::PCMPEQOp<2>},
{0x76, 1, &OpDispatchBuilder::PCMPEQOp<4>},
{0x77, 1, &OpDispatchBuilder::NOPOp},
{0xAE, 1, nullptr}, // GROUP 15
{0xB9, 1, nullptr}, // GROUP 10
{0xBA, 1, nullptr}, // GROUP 8
@@ -5278,6 +5464,46 @@ void InstallOpcodeHandlers() {
{0xC2, 1, &OpDispatchBuilder::VFCMPOp<4, false>},
{0xC6, 1, &OpDispatchBuilder::SHUFOp<4>},
{0xC7, 1, nullptr}, // GROUP 9
{0xD1, 1, &OpDispatchBuilder::PSRLDOp<2, true, 0>},
{0xD2, 1, &OpDispatchBuilder::PSRLDOp<4, true, 0>},
{0xD3, 1, &OpDispatchBuilder::PSRLDOp<8, true, 0>},
{0xD4, 1, &OpDispatchBuilder::PADDQOp<8>},
{0xD5, 1, &OpDispatchBuilder::PMULOp<2, true>},
{0xD8, 1, &OpDispatchBuilder::PSUBSOp<1, false>},
{0xD9, 1, &OpDispatchBuilder::PSUBSOp<2, false>},
{0xDA, 1, &OpDispatchBuilder::PMINUOp<1>},
{0xDB, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 8>},
{0xDC, 1, &OpDispatchBuilder::PADDSOp<1, false>},
{0xDD, 1, &OpDispatchBuilder::PADDSOp<2, false>},
{0xDE, 1, &OpDispatchBuilder::PMAXUOp<1>},
{0xDF, 1, &OpDispatchBuilder::ANDNOp},
{0xE1, 1, &OpDispatchBuilder::PSRAOp<2, true, 0>},
{0xE2, 1, &OpDispatchBuilder::PSRAOp<4, true, 0>},
{0xE4, 1, &OpDispatchBuilder::PMULHW<false>},
{0xE5, 1, &OpDispatchBuilder::PMULHW<true>},
{0xE7, 1, &OpDispatchBuilder::MOVUPSOp},
{0xE8, 1, &OpDispatchBuilder::PSUBSOp<1, true>},
{0xE9, 1, &OpDispatchBuilder::PSUBSOp<2, true>},
{0xEA, 1, &OpDispatchBuilder::PMINSWOp},
{0xEB, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 8>},
{0xEC, 1, &OpDispatchBuilder::PADDSOp<1, true>},
{0xED, 1, &OpDispatchBuilder::PADDSOp<2, true>},
{0xEE, 1, &OpDispatchBuilder::PMAXSWOp},
{0xEF, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 8>},
{0xF1, 1, &OpDispatchBuilder::PSLL<2, true, 0>},
{0xF2, 1, &OpDispatchBuilder::PSLL<4, true, 0>},
{0xF3, 1, &OpDispatchBuilder::PSLL<8, true, 0>},
{0xF4, 1, &OpDispatchBuilder::PMULLOp<4, false>},
{0xF5, 1, &OpDispatchBuilder::PMADDWD},
{0xF8, 1, &OpDispatchBuilder::PSUBQOp<1>},
{0xF9, 1, &OpDispatchBuilder::PSUBQOp<2>},
{0xFA, 1, &OpDispatchBuilder::PSUBQOp<4>},
{0xFB, 1, &OpDispatchBuilder::PSUBQOp<8>},
{0xFC, 1, &OpDispatchBuilder::PADDQOp<1>},
{0xFD, 1, &OpDispatchBuilder::PADDQOp<2>},
{0xFE, 1, &OpDispatchBuilder::PADDQOp<4>},
};
#define OPD(group, prefix, Reg) (((group - FEXCore::X86Tables::TYPE_GROUP_1) << 6) | (prefix) << 3 | (Reg))
@@ -5399,12 +5625,13 @@ void InstallOpcodeHandlers() {
{0x5E, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFDIV, 4>},
{0x5F, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMAX, 4>},
{0x6F, 1, &OpDispatchBuilder::MOVUPSOp},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, false>},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, true, false>},
{0x7E, 1, &OpDispatchBuilder::MOVQOp},
{0x7F, 1, &OpDispatchBuilder::MOVUPSOp},
{0xB8, 1, &OpDispatchBuilder::PopcountOp},
{0xBC, 2, &OpDispatchBuilder::TZCNT},
{0xC2, 1, &OpDispatchBuilder::VFCMPOp<4, true>},
{0xD6, 1, &OpDispatchBuilder::MOVQ2DQ<true>},
{0xE6, 1, &OpDispatchBuilder::Vector_CVT_Int_To_Float<4, true, true>},
};
@@ -5423,7 +5650,8 @@ void InstallOpcodeHandlers() {
{0x5D, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMIN, 8>},
{0x5E, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFDIV, 8>},
{0x5F, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMAX, 8>},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, true>},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<2, true, true>},
{0xD6, 1, &OpDispatchBuilder::MOVQ2DQ<false>},
{0xC2, 1, &OpDispatchBuilder::VFCMPOp<8, true>},
{0xF0, 1, &OpDispatchBuilder::MOVVectorOp},
};
@@ -5456,6 +5684,7 @@ void InstallOpcodeHandlers() {
{0x60, 1, &OpDispatchBuilder::PUNPCKLOp<1>},
{0x61, 1, &OpDispatchBuilder::PUNPCKLOp<2>},
{0x62, 1, &OpDispatchBuilder::PUNPCKLOp<4>},
{0x63, 1, &OpDispatchBuilder::PACKSSOp<2>},
{0x64, 1, &OpDispatchBuilder::PCMPGTOp<1>},
{0x65, 1, &OpDispatchBuilder::PCMPGTOp<2>},
{0x66, 1, &OpDispatchBuilder::PCMPGTOp<4>},
@@ -5463,11 +5692,12 @@ void InstallOpcodeHandlers() {
{0x68, 1, &OpDispatchBuilder::PUNPCKHOp<1>},
{0x69, 1, &OpDispatchBuilder::PUNPCKHOp<2>},
{0x6A, 1, &OpDispatchBuilder::PUNPCKHOp<4>},
{0x6B, 1, &OpDispatchBuilder::PACKSSOp<4>},
{0x6C, 1, &OpDispatchBuilder::PUNPCKLOp<8>},
{0x6D, 1, &OpDispatchBuilder::PUNPCKHOp<8>},
{0x6E, 1, &OpDispatchBuilder::MOVBetweenGPR_FPR},
{0x6F, 1, &OpDispatchBuilder::MOVUPSOp},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<4, true>},
{0x70, 1, &OpDispatchBuilder::PSHUFDOp<4, false, true>},
{0x74, 1, &OpDispatchBuilder::PCMPEQOp<1>},
{0x75, 1, &OpDispatchBuilder::PCMPEQOp<2>},
@@ -5493,6 +5723,8 @@ void InstallOpcodeHandlers() {
{0xDF, 1, &OpDispatchBuilder::ANDNOp},
{0xE1, 1, &OpDispatchBuilder::PSRAOp<2, true, 0>},
{0xE2, 1, &OpDispatchBuilder::PSRAOp<4, true, 0>},
{0xE4, 1, &OpDispatchBuilder::PMULHW<false>},
{0xE5, 1, &OpDispatchBuilder::PMULHW<true>},
{0xE6, 1, &OpDispatchBuilder::Vector_CVT_Float_To_Int<8, true, true>},
{0xE7, 1, &OpDispatchBuilder::MOVVectorOp},
{0xEA, 1, &OpDispatchBuilder::PMINSWOp},
@@ -5502,9 +5734,11 @@ void InstallOpcodeHandlers() {
{0xEE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSMAX, 2>},
{0xEF, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
{0xF1, 1, &OpDispatchBuilder::PSLL<2, true, 0>},
{0xF2, 1, &OpDispatchBuilder::PSLL<4, true, 0>},
{0xF3, 1, &OpDispatchBuilder::PSLL<8, true, 0>},
{0xF4, 1, &OpDispatchBuilder::PMULLOp<4, false>},
{0xF5, 1, &OpDispatchBuilder::PMADDWD},
{0xF8, 1, &OpDispatchBuilder::PSUBQOp<1>},
{0xF9, 1, &OpDispatchBuilder::PSUBQOp<2>},
{0xFA, 1, &OpDispatchBuilder::PSUBQOp<4>},
@@ -5542,16 +5776,27 @@ constexpr uint16_t PF_F2 = 3;
{OPD(FEXCore::X86Tables::TYPE_GROUP_8, PF_F2, 7), 1, &OpDispatchBuilder::BTCOp<1>},
// GROUP 12
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLI<2>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAIOp<2>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 6), 1, &OpDispatchBuilder::PSLLI<2>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 2), 1, &OpDispatchBuilder::PSRLI<2>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 4), 1, &OpDispatchBuilder::PSRAIOp<2>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 6), 1, &OpDispatchBuilder::PSLLI<2>},
// GROUP 13
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLI<4>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAIOp<4>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 6), 1, &OpDispatchBuilder::PSLLI<4>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 2), 1, &OpDispatchBuilder::PSRLI<4>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 4), 1, &OpDispatchBuilder::PSRAIOp<4>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 6), 1, &OpDispatchBuilder::PSLLI<4>},
// GROUP 14
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLI<8>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_NONE, 6), 1, &OpDispatchBuilder::PSLLI<8>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 2), 1, &OpDispatchBuilder::PSRLI<8>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 3), 1, &OpDispatchBuilder::PSRLDQ},
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 6), 1, &OpDispatchBuilder::PSLLI<8>},
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
Vendored
+19 -1
View File
@@ -214,13 +214,14 @@ public:
template<size_t ElementSize>
void PMAXUOp(OpcodeArgs);
void PMINSWOp(OpcodeArgs);
void PMAXSWOp(OpcodeArgs);
template<size_t ElementSize>
void MOVMSKOp(OpcodeArgs);
template<size_t ElementSize>
void PUNPCKLOp(OpcodeArgs);
template<size_t ElementSize>
void PUNPCKHOp(OpcodeArgs);
template<size_t ElementSize, bool Low>
template<size_t ElementSize, bool HalfSize, bool Low>
void PSHUFDOp(OpcodeArgs);
template<size_t ElementSize>
void PCMPEQOp(OpcodeArgs);
@@ -289,9 +290,26 @@ public:
template<size_t ElementSize>
void PACKUSOp(OpcodeArgs);
template<size_t ElementSize>
void PACKSSOp(OpcodeArgs);
template<size_t ElementSize, bool Signed>
void PMULLOp(OpcodeArgs);
template<bool ToXMM>
void MOVQ2DQ(OpcodeArgs);
template<size_t ElementSize, bool Signed>
void PADDSOp(OpcodeArgs);
template<size_t ElementSize, bool Signed>
void PSUBSOp(OpcodeArgs);
void PMADDWD(OpcodeArgs);
template<bool Signed>
void PMULHW(OpcodeArgs);
void UnimplementedOp(OpcodeArgs);
#undef OpcodeArgs
External/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp
Vendored
+8 -8
View File
@@ -212,11 +212,11 @@ void InitializeSecondaryGroupTables() {
// GROUP 12
{OPD(TYPE_GROUP_12, PF_NONE, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 1), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 2), 1, X86InstInfo{"PSRLW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 2), 1, X86InstInfo{"PSRLW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 3), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 4), 1, X86InstInfo{"PSRAW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 4), 1, X86InstInfo{"PSRAW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 5), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 6), 1, X86InstInfo{"PSLLW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 6), 1, X86InstInfo{"PSLLW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_12, PF_NONE, 7), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_12, PF_66, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
@@ -249,11 +249,11 @@ void InitializeSecondaryGroupTables() {
// GROUP 13
{OPD(TYPE_GROUP_13, PF_NONE, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 1), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 2), 1, X86InstInfo{"PSRLD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 2), 1, X86InstInfo{"PSRLD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 3), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 4), 1, X86InstInfo{"PSRAD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 4), 1, X86InstInfo{"PSRAD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 5), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 6), 1, X86InstInfo{"PSLLD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 6), 1, X86InstInfo{"PSLLD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_13, PF_NONE, 7), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_13, PF_66, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
@@ -286,11 +286,11 @@ void InitializeSecondaryGroupTables() {
// GROUP 14
{OPD(TYPE_GROUP_14, PF_NONE, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 1), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 2), 1, X86InstInfo{"PSRLQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 2), 1, X86InstInfo{"PSRLQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 3), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 4), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 5), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 6), 1, X86InstInfo{"PSLLQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 6), 1, X86InstInfo{"PSLLQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{OPD(TYPE_GROUP_14, PF_NONE, 7), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_14, PF_66, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
External/FEXCore/Source/Interface/Core/X86Tables/SecondaryTables.cpp
Vendored
+76 -76
View File
@@ -21,7 +21,7 @@ void InitializeSecondaryTables() {
{0x0B, 1, X86InstInfo{"UD2", TYPE_INST, FLAGS_DEBUG | FLAGS_BLOCK_END | FLAGS_NO_OVERLAY, 0, nullptr}},
{0x0C, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NO_OVERLAY, 0, nullptr}},
{0x0D, 1, X86InstInfo{"", TYPE_GROUP_P, FLAGS_NO_OVERLAY, 0, nullptr}},
{0x0E, 1, X86InstInfo{"FEMMS", TYPE_3DNOW_INST, FLAGS_BLOCK_END | FLAGS_NO_OVERLAY, 0, nullptr}},
{0x0E, 1, X86InstInfo{"FEMMS", TYPE_INST, FLAGS_BLOCK_END | FLAGS_NO_OVERLAY, 0, nullptr}},
{0x0F, 1, X86InstInfo{"", TYPE_3DNOW_TABLE, FLAGS_NO_OVERLAY, 0, nullptr}},
{0x10, 1, X86InstInfo{"MOVUPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
@@ -93,33 +93,33 @@ void InitializeSecondaryTables() {
{0x5E, 1, X86InstInfo{"DIVPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x5F, 1, X86InstInfo{"MAXPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x60, 1, X86InstInfo{"PUNPCKLBW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x61, 1, X86InstInfo{"PUNPCKLWD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x62, 1, X86InstInfo{"PUNPCKLDQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x63, 1, X86InstInfo{"PACKSSWB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x64, 1, X86InstInfo{"PCMPGTB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x65, 1, X86InstInfo{"PCMPGTW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x66, 1, X86InstInfo{"PCMPGTD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x67, 1, X86InstInfo{"PACKUSWB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x68, 1, X86InstInfo{"PUNPCKHBW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x69, 1, X86InstInfo{"PUNPCKHBD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x6A, 1, X86InstInfo{"PUNPCKHDQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x6B, 1, X86InstInfo{"PACKSSDW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x60, 1, X86InstInfo{"PUNPCKLBW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x61, 1, X86InstInfo{"PUNPCKLWD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x62, 1, X86InstInfo{"PUNPCKLDQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x63, 1, X86InstInfo{"PACKSSWB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x64, 1, X86InstInfo{"PCMPGTB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x65, 1, X86InstInfo{"PCMPGTW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x66, 1, X86InstInfo{"PCMPGTD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x67, 1, X86InstInfo{"PACKUSWB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x68, 1, X86InstInfo{"PUNPCKHBW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x69, 1, X86InstInfo{"PUNPCKHBD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x6A, 1, X86InstInfo{"PUNPCKHDQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x6B, 1, X86InstInfo{"PACKSSDW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x6C, 2, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0x6E, 1, X86InstInfo{"MOVD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x6F, 1, X86InstInfo{"MOVQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x6E, 1, X86InstInfo{"MOVD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_SRC_GPR | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x6F, 1, X86InstInfo{"MOVQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x70, 1, X86InstInfo{"PSHUFW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
{0x70, 1, X86InstInfo{"PSHUFW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{0x71, 1, X86InstInfo{"", TYPE_GROUP_12, FLAGS_NONE, 0, nullptr}},
{0x72, 1, X86InstInfo{"", TYPE_GROUP_13, FLAGS_NONE, 0, nullptr}},
{0x73, 1, X86InstInfo{"", TYPE_GROUP_14, FLAGS_NONE, 0, nullptr}},
{0x74, 1, X86InstInfo{"PCMPEQB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x75, 1, X86InstInfo{"PCMPEQW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x76, 1, X86InstInfo{"PCMPEQD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x77, 1, X86InstInfo{"EMMS", TYPE_3DNOW_INST, FLAGS_NONE, 0, nullptr}},
{0x74, 1, X86InstInfo{"PCMPEQB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x75, 1, X86InstInfo{"PCMPEQW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x76, 1, X86InstInfo{"PCMPEQD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x77, 1, X86InstInfo{"EMMS", TYPE_INST, FLAGS_NONE, 0, nullptr}},
{0x78, 6, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0x7E, 1, X86InstInfo{"MOVD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x7F, 1, X86InstInfo{"MOVQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
{0x7E, 1, X86InstInfo{"MOVD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x7F, 1, X86InstInfo{"MOVQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0x80, 1, X86InstInfo{"JO", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_NO_OVERLAY, 4, nullptr}},
{0x81, 1, X86InstInfo{"JNO", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2 | FLAGS_NO_OVERLAY, 4, nullptr}},
@@ -188,65 +188,65 @@ void InitializeSecondaryTables() {
{0xBE, 1, X86InstInfo{"MOVSX", TYPE_INST, GenFlagsSrcSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_NO_OVERLAY, 0, nullptr}},
{0xBF, 1, X86InstInfo{"MOVSX", TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_MODRM | FLAGS_NO_OVERLAY, 0, nullptr}},
{0xC0, 1, X86InstInfo{"XADD", TYPE_INST, GenFlagsSrcSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST, 0, nullptr}},
{0xC1, 1, X86InstInfo{"XADD", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY, 0, nullptr}},
{0xC2, 1, X86InstInfo{"CMPPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
{0xC3, 1, X86InstInfo{"MOVNTI", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_SF_MOD_DST, 0, nullptr}},
{0xC4, 1, X86InstInfo{"PINSRW", TYPE_MMX, GenFlagsSizes(SIZE_64BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 1, nullptr}},
{0xC5, 1, X86InstInfo{"PEXTRW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_XMM_FLAGS, 1, nullptr}},
{0xC6, 1, X86InstInfo{"SHUFPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
{0xC7, 1, X86InstInfo{"", TYPE_GROUP_9, FLAGS_NONE, 0, nullptr}},
{0xC8, 8, X86InstInfo{"BSWAP", TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_NO_OVERLAY, 0, nullptr}},
{0xC0, 1, X86InstInfo{"XADD", TYPE_INST, GenFlagsSrcSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST, 0, nullptr}},
{0xC1, 1, X86InstInfo{"XADD", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY, 0, nullptr}},
{0xC2, 1, X86InstInfo{"CMPPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
{0xC3, 1, X86InstInfo{"MOVNTI", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_SF_MOD_DST, 0, nullptr}},
{0xC4, 1, X86InstInfo{"PINSRW", TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX | FLAGS_SF_SRC_GPR, 1, nullptr}},
{0xC5, 1, X86InstInfo{"PEXTRW", TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_REG_ONLY | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
{0xC6, 1, X86InstInfo{"SHUFPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
{0xC7, 1, X86InstInfo{"", TYPE_GROUP_9, FLAGS_NONE, 0, nullptr}},
{0xC8, 8, X86InstInfo{"BSWAP", TYPE_INST, FLAGS_SF_REX_IN_BYTE | FLAGS_NO_OVERLAY, 0, nullptr}},
{0xD0, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xD1, 1, X86InstInfo{"PSRLW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD2, 1, X86InstInfo{"PSRLD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD3, 1, X86InstInfo{"PSRLQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD4, 1, X86InstInfo{"PADDQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}}, // SSE2 extending MMX
{0xD5, 1, X86InstInfo{"PMULLW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD1, 1, X86InstInfo{"PSRLW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xD2, 1, X86InstInfo{"PSRLD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xD3, 1, X86InstInfo{"PSRLQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xD4, 1, X86InstInfo{"PADDQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xD5, 1, X86InstInfo{"PMULLW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xD6, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xD7, 1, X86InstInfo{"PMOVMSKB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_DST_GPR, 0, nullptr}},
{0xD8, 1, X86InstInfo{"PSUBUSB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD9, 1, X86InstInfo{"PSUBUSW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xDA, 1, X86InstInfo{"PMINUB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xDB, 1, X86InstInfo{"PAND", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xDC, 1, X86InstInfo{"PADDUSB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xDD, 1, X86InstInfo{"PADDUSW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xDE, 1, X86InstInfo{"PMAXUB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xDF, 1, X86InstInfo{"PANDN", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD7, 1, X86InstInfo{"PMOVMSKB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_DST_GPR, 0, nullptr}},
{0xD8, 1, X86InstInfo{"PSUBUSB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xD9, 1, X86InstInfo{"PSUBUSW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xDA, 1, X86InstInfo{"PMINUB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xDB, 1, X86InstInfo{"PAND", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xDC, 1, X86InstInfo{"PADDUSB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xDD, 1, X86InstInfo{"PADDUSW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xDE, 1, X86InstInfo{"PMAXUB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xDF, 1, X86InstInfo{"PANDN", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE0, 1, X86InstInfo{"PAVGB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE1, 1, X86InstInfo{"PSRAW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE2, 1, X86InstInfo{"PSRAD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE3, 1, X86InstInfo{"PAVGW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE4, 1, X86InstInfo{"PMULHUW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE5, 1, X86InstInfo{"PMULHW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE0, 1, X86InstInfo{"PAVGB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE1, 1, X86InstInfo{"PSRAW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE2, 1, X86InstInfo{"PSRAD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE3, 1, X86InstInfo{"PAVGW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE4, 1, X86InstInfo{"PMULHUW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE5, 1, X86InstInfo{"PMULHW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE6, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xE7, 1, X86InstInfo{"MOVNTQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE8, 1, X86InstInfo{"PSUBSB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE9, 1, X86InstInfo{"PSUBSW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xEA, 1, X86InstInfo{"PMINSW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xEB, 1, X86InstInfo{"POR", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xEC, 1, X86InstInfo{"PADDSB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xED, 1, X86InstInfo{"PADDSW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xEE, 1, X86InstInfo{"PMAXSW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xEF, 1, X86InstInfo{"PXOR", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xE7, 1, X86InstInfo{"MOVNTQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE8, 1, X86InstInfo{"PSUBSB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xE9, 1, X86InstInfo{"PSUBSW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xEA, 1, X86InstInfo{"PMINSW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xEB, 1, X86InstInfo{"POR", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xEC, 1, X86InstInfo{"PADDSB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xED, 1, X86InstInfo{"PADDSW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xEE, 1, X86InstInfo{"PMAXSW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xEF, 1, X86InstInfo{"PXOR", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF0, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xF1, 1, X86InstInfo{"PSLLW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF2, 1, X86InstInfo{"PSLLD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF3, 1, X86InstInfo{"PSLLQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF4, 1, X86InstInfo{"PMULUDQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF5, 1, X86InstInfo{"PMADDWD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF6, 1, X86InstInfo{"PSADBW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF7, 1, X86InstInfo{"MASKMOVQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF8, 1, X86InstInfo{"PSUBB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF9, 1, X86InstInfo{"PSUBW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xFA, 1, X86InstInfo{"PSUBD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xFB, 1, X86InstInfo{"PSUBQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xFC, 1, X86InstInfo{"PADDB", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xFD, 1, X86InstInfo{"PADDW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xFE, 1, X86InstInfo{"PADDD", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xF1, 1, X86InstInfo{"PSLLW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF2, 1, X86InstInfo{"PSLLD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF3, 1, X86InstInfo{"PSLLQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF4, 1, X86InstInfo{"PMULUDQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF5, 1, X86InstInfo{"PMADDWD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF6, 1, X86InstInfo{"PSADBW", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF7, 1, X86InstInfo{"MASKMOVQ", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF8, 1, X86InstInfo{"PSUBB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xF9, 1, X86InstInfo{"PSUBW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xFA, 1, X86InstInfo{"PSUBD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xFB, 1, X86InstInfo{"PSUBQ", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xFC, 1, X86InstInfo{"PADDB", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xFD, 1, X86InstInfo{"PADDW", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xFE, 1, X86InstInfo{"PADDD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
{0xFF, 1, X86InstInfo{"UD0", TYPE_INST, FLAGS_DEBUG | FLAGS_BLOCK_END, 0, nullptr}},
};
@@ -316,7 +316,7 @@ void InitializeSecondaryTables() {
{0xC8, 8, X86InstInfo{"", TYPE_COPY_OTHER, FLAGS_NONE, 0, nullptr}},
{0xD0, 6, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xD6, 1, X86InstInfo{"MOVQ2DQ", TYPE_MMX, GenFlagsSameSize(SIZE_128BIT) | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD6, 1, X86InstInfo{"MOVQ2DQ", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX_SRC, 0, nullptr}},
{0xD7, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xD8, 8, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
@@ -389,7 +389,7 @@ void InitializeSecondaryTables() {
{0xD0, 1, X86InstInfo{"ADDSUBPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD1, 5, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xD6, 1, X86InstInfo{"MOVDQ2Q", TYPE_MMX, GenFlagsSameSize(SIZE_64BIT) | FLAGS_XMM_FLAGS, 0, nullptr}},
{0xD6, 1, X86InstInfo{"MOVDQ2Q", TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX_DST, 0, nullptr}},
{0xD7, 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{0xD8, 8, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
External/FEXCore/Source/Interface/IR/IR.json
Vendored
+9
View File
@@ -627,6 +627,15 @@
"SSAArgs": "1"
},
"VMov": {
"HasDest": true,
"DestSize": "RegisterSize",
"SSAArgs": "1",
"Args": [
"uint8_t", "RegisterSize"
]
},
"VAnd": {
"HasDest": true,
"SSAArgs": "2",
unittests/ASM/OpSize/66_63.asm
+37
View File
@@ -0,0 +1,37 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x00807F4100807F41", "0x00FF7F4100FF7F41"],
"XMM1": ["0x00807F4100807F41", "0x00FF7F4100FF7F41"],
"XMM2": ["0x0000FFFF007F0041", "0x0000FFFF007F0041"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
; 16bit signed -> 8bit signed (saturated)
; input > 0x7F(SCHAR_MAX, 127) = 0x7F(SCHAR_MAX, 127)
; input < 0x80(-127) = 0x80
mov rax, 0x00008000007F0041
mov [rdx + 8 * 0], rax
mov rax, 0x00008000007F0041
mov [rdx + 8 * 1], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 2], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx]
packsswb xmm0, [rdx + 8 * 2]
movapd xmm1, [rdx]
movapd xmm2, [rdx + 8 * 2]
packsswb xmm1, xmm2
hlt
unittests/ASM/OpSize/66_6B.asm
+37
View File
@@ -0,0 +1,37 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x00000040FFFF8000", "0x00000040FFFF8000"],
"XMM1": ["0x00000040FFFF8000", "0x00000040FFFF8000"],
"XMM2": ["0xFFFFFFFF80000000", "0x0000000000000040"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
; 32bit signed -> 16bit signed (saturated)
; input > 0x7FFF(SHRT_MAX, 32767) = 0x7FFF(SHRT_MAX, 32767)
; input < 0x8000(-32767) = 0x8000
mov rax, 0xFFFFFFFF80000000
mov [rdx + 8 * 0], rax
mov rax, 0x0000000000000040
mov [rdx + 8 * 1], rax
mov rax, 0xFFFFFFFF80000000
mov [rdx + 8 * 2], rax
mov rax, 0x0000000000000040
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx]
packssdw xmm0, [rdx + 8 * 2]
movapd xmm1, [rdx]
movapd xmm2, [rdx + 8 * 2]
packssdw xmm1, xmm2
hlt
unittests/ASM/OpSize/66_E4.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x18D21A1D1B701CCA", "0x24092594272728C2"],
"XMM1": ["0x18D21A1D1B701CCA", "0x24092594272728C2"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx + 8 * 0]
movapd xmm1, [rdx + 8 * 0]
movapd xmm2, [rdx + 8 * 2]
pmulhuw xmm0, xmm2
pmulhuw xmm1, [rdx + 8 * 2]
hlt
unittests/ASM/OpSize/66_E5.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x18D21A1D1B70CF3C", "0x24092594272728C2"],
"XMM1": ["0x18D21A1D1B70CF3C", "0x24092594272728C2"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445468748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx + 8 * 0]
movapd xmm1, [rdx + 8 * 0]
movapd xmm2, [rdx + 8 * 2]
pmulhw xmm0, xmm2
pmulhw xmm1, [rdx + 8 * 2]
hlt
unittests/ASM/OpSize/66_F1.asm
+52
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@@ -0,0 +1,52 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x828486888A8C8E90", "0xE2E4E6E8EAECEEF0"],
"XMM1": ["0x4200440046004800", "0x7200740076007800"],
"XMM2": ["0x0", "0x0"],
"XMM3": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 7], rax
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 9], rax
movaps xmm0, [rdx + 8 * 0]
movaps xmm1, [rdx + 8 * 0]
movaps xmm2, [rdx + 8 * 0]
movaps xmm3, [rdx + 8 * 0]
psllw xmm0, [rdx + 8 * 2]
psllw xmm1, [rdx + 8 * 4]
psllw xmm2, [rdx + 8 * 6]
psllw xmm3, [rdx + 8 * 8]
hlt
unittests/ASM/OpSize/66_F5.asm
+35
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@@ -0,0 +1,35 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x32F08FD4383B2524", "0x499DE6944FEA7CE4"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov eax, dword [rdx + 8 * 0]
mov rbx, qword [rdx + 8 * 1]
movaps xmm0, [rdx + 8 * 0]
pmaddwd xmm0, [rdx + 8 * 2]
hlt
unittests/ASM/REP/F3_D6.asm
+34
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@@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"XMM0": ["0x4142434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
movaps xmm0, [rdx + 8 * 2]
movq mm0, [rdx + 8 * 0]
movq2dq xmm0, mm0
hlt
unittests/ASM/REPNE/F2_D6.asm
+34
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@@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"XMM0": ["0x4142434445464748", "0x5152535455565758"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
movaps xmm0, [rdx + 8 * 0]
movq mm0, [rdx + 8 * 2]
movdq2q mm0, xmm0
hlt
unittests/ASM/TwoByte/0F_0E.asm
+13
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@@ -0,0 +1,13 @@
%ifdef CONFIG
{
"RegData": {
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
femms ; Just ensure it runs
hlt
unittests/ASM/TwoByte/0F_2B.asm
+29
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@@ -0,0 +1,29 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x4142434445464748", "0x5152535455565758"],
"XMM1": ["0x4142434445464748", "0x5152535455565758"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x0
mov [rdx + 8 * 2], rax
mov [rdx + 8 * 3], rax
movaps xmm0, [rdx + 8 * 0]
movntps [rdx + 8 * 2], xmm0
movaps xmm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_60.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6545664667476848", "0x0"],
"MM1": ["0x6545664667476848", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
punpcklbw mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
punpcklbw mm1, mm2
hlt
unittests/ASM/TwoByte/0F_61.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6566454667684748", "0x0"],
"MM1": ["0x6566454667684748", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
punpcklwd mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
punpcklwd mm1, mm2
hlt
unittests/ASM/TwoByte/0F_62.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6566676845464748", "0x0"],
"MM1": ["0x6566676845464748", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
punpckldq mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
punpckldq mm1, mm2
hlt
unittests/ASM/TwoByte/0F_63.asm
+37
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@@ -0,0 +1,37 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x00FF7F4100807F41", "0x0"],
"MM1": ["0x00FF7F4100807F41", "0x0"],
"MM2": ["0x0000FFFF007F0041", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
; 16bit signed -> 8bit signed (saturated)
; input > 0x7F(SCHAR_MAX, 127) = 0x7F(SCHAR_MAX, 127)
; input < 0x80(-127) = 0x80
mov rax, 0x00008000007F0041
mov [rdx + 8 * 0], rax
mov rax, 0x00008000007F0041
mov [rdx + 8 * 1], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 2], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
packsswb mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
packsswb mm1, mm2
hlt
unittests/ASM/TwoByte/0F_64.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xFFFFFFFFFFFFFFFF", "0x0"],
"MM1": ["0xFFFFFFFFFFFFFFFF", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x7172737475767778
mov [rdx + 8 * 0], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pcmpgtb mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pcmpgtb mm1, mm2
hlt
unittests/ASM/TwoByte/0F_65.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xFFFFFFFFFFFFFFFF", "0x0"],
"MM1": ["0xFFFFFFFFFFFFFFFF", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x7172737475767778
mov [rdx + 8 * 0], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pcmpgtw mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pcmpgtw mm1, mm2
hlt
unittests/ASM/TwoByte/0F_66.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xFFFFFFFFFFFFFFFF", "0x0"],
"MM1": ["0xFFFFFFFFFFFFFFFF", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x7172737475767778
mov [rdx + 8 * 0], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pcmpgtd mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pcmpgtd mm1, mm2
hlt
unittests/ASM/TwoByte/0F_67.asm
+37
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@@ -0,0 +1,37 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x00007F4100007F41", "0x0"],
"MM1": ["0x00007F4100007F41", "0x0"],
"MM2": ["0x0000FFFF007F0041", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
; 16bit signed -> 8bit unsigned (saturated)
; input > 0x7F(SCHAR_MAX, 127) = 0xFF(UCHAR_MAX, 255)
; input < 0x00(Negative) = 0x0
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 0], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 1], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 2], rax
mov rax, 0x0000FFFF007F0041
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
packuswb mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
packuswb mm1, mm2
hlt
unittests/ASM/TwoByte/0F_68.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6141624263436444", "0x0"],
"MM1": ["0x6141624263436444", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
punpckhbw mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
punpckhbw mm1, mm2
hlt
unittests/ASM/TwoByte/0F_69.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6162414263644344", "0x0"],
"MM1": ["0x6162414263644344", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
punpckhwd mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
punpckhwd mm1, mm2
hlt
unittests/ASM/TwoByte/0F_6A.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6162636441424344", "0x0"],
"MM1": ["0x6162636441424344", "0x0"],
"MM2": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
punpckhdq mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
punpckhdq mm1, mm2
hlt
unittests/ASM/TwoByte/0F_6B.asm
+37
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@@ -0,0 +1,37 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xFFFF8000FFFF8000", "0x0"],
"MM1": ["0xFFFF8000FFFF8000", "0x0"],
"MM2": ["0xFFFFFFFF80000000", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
; 32bit signed -> 16bit signed (saturated)
; input > 0x7FFF(SHRT_MAX, 32767) = 0x7FFF(SHRT_MAX, 32767)
; input < 0x8000(-32767) = 0x8000
mov rax, 0xFFFFFFFF80000000
mov [rdx + 8 * 0], rax
mov rax, 0x0000000000000040
mov [rdx + 8 * 1], rax
mov rax, 0xFFFFFFFF80000000
mov [rdx + 8 * 2], rax
mov rax, 0x0000000000000040
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
packssdw mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
packssdw mm1, mm2
hlt
unittests/ASM/TwoByte/0F_6E.asm
+34
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@@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x0000000045464748", "0x0"],
"MM1": ["0x5152535455565758", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov eax, dword [rdx + 8 * 0]
mov rbx, qword [rdx + 8 * 1]
movd mm0, eax
movq mm1, rbx
hlt
unittests/ASM/TwoByte/0F_6F.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4142434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 1]
movq mm1, mm0
hlt
unittests/ASM/TwoByte/0F_70.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x6162636465666768", "0x0"],
"MM2": ["0x4748474847484748", "0x0"],
"MM3": ["0x6162616261626162", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
movq mm1, [rdx + 8 * 2]
pshufw mm2, mm0, 0x0
pshufw mm3, mm1, 0xFF
hlt
unittests/ASM/TwoByte/0F_74.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x00000000000000FF", "0x0"],
"MM1": ["0x00000000000000FF", "0x0"],
"MM2": ["0x6162636465666778", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x7172737475767778
mov [rdx + 8 * 0], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666778
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565748
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pcmpeqb mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pcmpeqb mm1, mm2
hlt
unittests/ASM/TwoByte/0F_75.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x000000000000FFFF", "0x0"],
"MM1": ["0x000000000000FFFF", "0x0"],
"MM2": ["0x6162636465667778", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x7172737475767778
mov [rdx + 8 * 0], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465667778
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455564748
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pcmpeqw mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pcmpeqw mm1, mm2
hlt
unittests/ASM/TwoByte/0F_76.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x00000000FFFFFFFF", "0x0"],
"MM1": ["0x00000000FFFFFFFF", "0x0"],
"MM2": ["0x61626364FFFFFFFF", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x71727374FFFFFFFF
mov [rdx + 8 * 0], rax
mov rax, 0x41424344FFFFFFFF
mov [rdx + 8 * 1], rax
mov rax, 0x61626364FFFFFFFF
mov [rdx + 8 * 2], rax
mov rax, 0x51525354FFFFFFFF
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pcmpeqd mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pcmpeqd mm1, mm2
hlt
unittests/ASM/TwoByte/0F_77.asm
+13
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@@ -0,0 +1,13 @@
%ifdef CONFIG
{
"RegData": {
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
emms ; Just ensure it runs
hlt
unittests/ASM/TwoByte/0F_7E.asm
+41
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@@ -0,0 +1,41 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x0000000045464748",
"RBX": "0x5152535455565758"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov eax, dword [rdx + 8 * 0]
mov rbx, qword [rdx + 8 * 1]
movd mm0, eax
movq mm1, rbx
mov rax, 0
mov rbx, 0
movd eax, mm0
movq rbx, mm1
hlt
unittests/ASM/TwoByte/0F_7F.asm
+34
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@@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4142434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 1]
movq [rdx + 8 * 4], mm0
movq mm1, [rdx + 8 * 4]
hlt
unittests/ASM/TwoByte/0F_C3.asm
+29
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@@ -0,0 +1,29 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x4142434445464748",
"RBX": "0x4142434445464748",
"RCX": "0x0000000045464748"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x0
mov [rdx + 8 * 1], rax
mov [rdx + 8 * 2], rax
mov rax, [rdx + 8 * 0]
movnti [rdx + 8 * 1], rax
movnti [rdx + 8 * 2], eax
mov rbx, [rdx + 8 * 1]
mov rcx, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_C4.asm
+48
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@@ -0,0 +1,48 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445467778", "0x0"],
"MM1": ["0x4142434477784748", "0x0"],
"MM2": ["0x4142777845464748", "0x0"],
"MM3": ["0x7778434445464748", "0x0"],
"MM4": ["0x4142434445467778", "0x0"],
"MM5": ["0x4142434477784748", "0x0"],
"MM6": ["0x4142777845464748", "0x0"],
"MM7": ["0x7778434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 2], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
movq mm5, [rdx + 8 * 0]
movq mm6, [rdx + 8 * 0]
movq mm7, [rdx + 8 * 0]
pinsrw mm0, eax, 0
pinsrw mm1, eax, 1
pinsrw mm2, eax, 2
pinsrw mm3, eax, 3
pinsrw mm4, [rdx + 8 * 2], 0
pinsrw mm5, [rdx + 8 * 2], 1
pinsrw mm6, [rdx + 8 * 2], 2
pinsrw mm7, [rdx + 8 * 2], 3
hlt
unittests/ASM/TwoByte/0F_C5.asm
+34
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@@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x4748",
"RBX": "0x4546",
"RCX": "0x4344",
"RDX": "0x4142"
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
movq mm0, [rdx + 8 * 0]
mov rax, -1
mov rbx, -1
mov rcx, -1
mov rdx, -1
pextrw eax, mm0, 0
pextrw ebx, mm0, 1
pextrw ecx, mm0, 2
pextrw edx, mm0, 3
hlt
unittests/ASM/TwoByte/0F_D1.asm
+63
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@@ -0,0 +1,63 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x20A121A222A323A4", "0x0"],
"MM1": ["0x0041004300450047", "0x0"],
"MM2": ["0x0", "0x0"],
"MM3": ["0x0", "0x0"],
"MM4": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x0
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x0
mov [rdx + 8 * 5], rax
; Will Zero
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x0
mov [rdx + 8 * 7], rax
; Will Zero
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x0
mov [rdx + 8 * 9], rax
; Will Zero
mov rax, 0x40
mov [rdx + 8 * 10], rax
mov rax, 0x0
mov [rdx + 8 * 11], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
psrlw mm0, [rdx + 8 * 2]
psrlw mm1, [rdx + 8 * 4]
psrlw mm2, [rdx + 8 * 6]
psrlw mm3, [rdx + 8 * 8]
psrlw mm4, [rdx + 8 * 10]
hlt
unittests/ASM/TwoByte/0F_D2.asm
+62
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@@ -0,0 +1,62 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x20A121A222A323A4", "0x0"],
"MM1": ["0x0041424300454647", "0x0"],
"MM2": ["0x0000414200004546", "0x0"],
"MM3": ["0x0", "0x0"],
"MM4": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x0
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x0
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x0
mov [rdx + 8 * 7], rax
; Will Zero
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x0
mov [rdx + 8 * 9], rax
; Will Zero
mov rax, 0x40
mov [rdx + 8 * 10], rax
mov rax, 0x0
mov [rdx + 8 * 11], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
psrld mm0, [rdx + 8 * 2]
psrld mm1, [rdx + 8 * 4]
psrld mm2, [rdx + 8 * 6]
psrld mm3, [rdx + 8 * 8]
psrld mm4, [rdx + 8 * 10]
hlt
unittests/ASM/TwoByte/0F_D3.asm
+61
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@@ -0,0 +1,61 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x20A121A222A323A4", "0x0"],
"MM1": ["0x0041424344454647", "0x0"],
"MM2": ["0x0000414243444546", "0x0"],
"MM3": ["0x0000000041424344", "0x0"],
"MM4": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x0
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x0
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x0
mov [rdx + 8 * 7], rax
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x0
mov [rdx + 8 * 9], rax
; Will Zero
mov rax, 0x40
mov [rdx + 8 * 10], rax
mov rax, 0x0
mov [rdx + 8 * 11], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
psrlq mm0, [rdx + 8 * 2]
psrlq mm1, [rdx + 8 * 4]
psrlq mm2, [rdx + 8 * 6]
psrlq mm3, [rdx + 8 * 8]
psrlq mm4, [rdx + 8 * 10]
hlt
unittests/ASM/TwoByte/0F_D5.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xFD44929037E4ED40", "0x0"],
"MM1": ["0xFD44929037E4ED40", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
pmullw mm0, mm2
pmullw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_D8.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2020202000000000", "0x0"],
"MM1": ["0x2020202000000000", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x6162636445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x4142434465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
psubusb mm0, mm2
psubusb mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_D9.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2020202000000000", "0x0"],
"MM1": ["0x2020202000000000", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x6162636445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x4142434465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
psubusw mm0, mm2
psubusw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_DA.asm
+25
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@@ -0,0 +1,25 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4142434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 1]
pminub mm0, mm1
pminub mm1, [rdx + 8 * 0]
hlt
unittests/ASM/TwoByte/0F_DB.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x1010101010101010", "0x0"],
"MM1": ["0x1010101010101010", "0x0"],
"MM2": ["0x1010101010101010", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0xFFFFFFFFFFFFFFFF
mov [rdx + 8 * 0], rax
mov rax, 0x0
mov [rdx + 8 * 1], rax
mov rax, 0x1010101010101010
mov [rdx + 8 * 2], rax
mov rax, 0xFFFFFFFFFFFFFFFF
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pand mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pand mm1, mm2
hlt
unittests/ASM/TwoByte/0F_DC.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xA2A4A6A8AAACAEB0", "0x0"],
"MM1": ["0xA2A4A6A8AAACAEB0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddusb mm0, mm2
paddusb mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_DD.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xA2A4A6A8AAACAEB0", "0x0"],
"MM1": ["0xA2A4A6A8AAACAEB0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddusw mm0, mm2
paddusw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_DE.asm
+25
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@@ -0,0 +1,25 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x5152535455565758", "0x0"],
"MM1": ["0x5152535455565758", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 1]
pmaxub mm0, mm1
pmaxub mm1, [rdx + 8 * 0]
hlt
unittests/ASM/TwoByte/0F_DF.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x0", "0x0"],
"MM1": ["0x0", "0x0"],
"MM2": ["0x1010101010101010", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0xFFFFFFFFFFFFFFFF
mov [rdx + 8 * 0], rax
mov rax, 0x0
mov [rdx + 8 * 1], rax
mov rax, 0x1010101010101010
mov [rdx + 8 * 2], rax
mov rax, 0xFFFFFFFFFFFFFFFF
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pandn mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pandn mm1, mm2
hlt
unittests/ASM/TwoByte/0F_E1.asm
+58
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@@ -0,0 +1,58 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x0041004300450047", "0x0"],
"MM2": ["0x0", "0x0"],
"MM3": ["0x4142434445464748", "0x0"],
"MM4": ["0x0041004300450047", "0x0"],
"MM5": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x0
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 7], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
movq mm5, [rdx + 8 * 0]
movq mm6, [rdx + 8 * 2]
movq mm7, [rdx + 8 * 4]
psraw mm0, mm6
psraw mm1, mm7
movq mm7, [rdx + 8 * 6]
psraw mm2, mm7
psraw mm3, [rdx + 8 * 2]
psraw mm4, [rdx + 8 * 4]
psraw mm5, [rdx + 8 * 6]
hlt
unittests/ASM/TwoByte/0F_E2.asm
+59
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@@ -0,0 +1,59 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x0000414200004546", "0x0"],
"MM2": ["0x0", "0x0"],
"MM3": ["0x4142434445464748", "0x0"],
"MM4": ["0x0000414200004546", "0x0"],
"MM5": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x0
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
mov rax, 0x10
mov [rdx + 8 * 4], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 5], rax
mov rax, 0x20
mov [rdx + 8 * 6], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 7], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
movq mm5, [rdx + 8 * 0]
movq mm6, [rdx + 8 * 2]
movq mm7, [rdx + 8 * 4]
psrad mm0, mm6
psrad mm1, mm7
movq mm7, [rdx + 8 * 6]
psrad mm2, mm7
psrad mm3, [rdx + 8 * 2]
psrad mm4, [rdx + 8 * 4]
psrad mm5, [rdx + 8 * 6]
hlt
unittests/ASM/TwoByte/0F_E4.asm
+35
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@@ -0,0 +1,35 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x14BA15E517171851", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov eax, dword [rdx + 8 * 0]
mov rbx, qword [rdx + 8 * 1]
movq mm0, [rdx + 8 * 0]
pmulhuw mm0, [rdx + 8 * 1]
hlt
unittests/ASM/TwoByte/0F_E5.asm
+35
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@@ -0,0 +1,35 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xD7D1D77A17171851", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x8182838445464748 ; -32382, -31868, 17734, 18248
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758 ; 20818, 21332, 21846, 22360
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov eax, dword [rdx + 8 * 0]
mov rbx, qword [rdx + 8 * 1]
movq mm0, [rdx + 8 * 0]
pmulhw mm0, [rdx + 8 * 1]
hlt
unittests/ASM/TwoByte/0F_E7.asm
+26
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@@ -0,0 +1,26 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4142434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x0
mov [rdx + 8 * 1], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 1]
movntq [rdx + 8 * 1], mm0
movq mm1, [rdx + 8 * 1]
hlt
unittests/ASM/TwoByte/0F_E8.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xE0E0E0E0E0E0E0E0", "0x0"],
"MM1": ["0xE0E0E0E0E0E0E0E0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
psubsb mm0, mm2
psubsb mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_E9.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xDFE0DFE0DFE0DFE0", "0x0"],
"MM1": ["0xDFE0DFE0DFE0DFE0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
psubsw mm0, mm2
psubsw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_EA.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4142434445464748", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
pminsw mm0, mm2
pminsw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_EB.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x1111111111111111", "0x0"],
"MM1": ["0x1111111111111111", "0x0"],
"MM2": ["0x0101010101010101", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x1010101010101010
mov [rdx + 8 * 0], rax
mov rax, 0x2020202020202020
mov [rdx + 8 * 1], rax
mov rax, 0x0101010101010101
mov [rdx + 8 * 2], rax
mov rax, 0x0202020202020202
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
por mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
por mm1, mm2
hlt
unittests/ASM/TwoByte/0F_EC.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x7F7F7F7F7F7F7F7F", "0x0"],
"MM1": ["0x7F7F7F7F7F7F7F7F", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddsb mm0, mm2
paddsb mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_ED.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x7FFF7FFF7FFF7FFF", "0x0"],
"MM1": ["0x7FFF7FFF7FFF7FFF", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddsw mm0, mm2
paddsw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_EE.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x6162636465666768", "0x0"],
"MM1": ["0x6162636465666768", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
pmaxsw mm0, mm2
pmaxsw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_EF.asm
+33
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@@ -0,0 +1,33 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2424242424242424", "0x0"],
"MM1": ["0x2424242424242424", "0x0"],
"MM2": ["0x1818181818181818", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x3C3C3C3C3C3C3C3C
mov [rdx + 8 * 0], rax
mov rax, 0x3C3C3C3C3C3C3C3C
mov [rdx + 8 * 1], rax
mov rax, 0x1818181818181818
mov [rdx + 8 * 2], rax
mov rax, 0x1818181818181818
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pxor mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pxor mm1, mm2
hlt
unittests/ASM/TwoByte/0F_F1.asm
+52
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@@ -0,0 +1,52 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x828486888A8C8E90", "0x0"],
"MM1": ["0x4200440046004800", "0x0"],
"MM2": ["0x0", "0x0"],
"MM3": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x1
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
mov rax, 0x8
mov [rdx + 8 * 4], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 5], rax
mov rax, 0x10
mov [rdx + 8 * 6], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 7], rax
mov rax, 0x20
mov [rdx + 8 * 8], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 9], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
psllw mm0, [rdx + 8 * 2]
psllw mm1, [rdx + 8 * 4]
psllw mm2, [rdx + 8 * 6]
psllw mm3, [rdx + 8 * 8]
hlt
unittests/ASM/TwoByte/0F_F2.asm
+59
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@@ -0,0 +1,59 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4344000047480000", "0x0"],
"MM2": ["0x0", "0x0"],
"MM3": ["0x4142434445464748", "0x0"],
"MM4": ["0x4344000047480000", "0x0"],
"MM5": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x0
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
mov rax, 0x10
mov [rdx + 8 * 4], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 5], rax
mov rax, 0x20
mov [rdx + 8 * 6], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 7], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
movq mm5, [rdx + 8 * 0]
movq mm6, [rdx + 8 * 2]
movq mm7, [rdx + 8 * 4]
pslld mm0, mm6
pslld mm1, mm7
movq mm7, [rdx + 8 * 6]
pslld mm2, mm7
pslld mm3, [rdx + 8 * 2]
pslld mm4, [rdx + 8 * 4]
pslld mm5, [rdx + 8 * 6]
hlt
unittests/ASM/TwoByte/0F_F3.asm
+58
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@@ -0,0 +1,58 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x4142434445464748", "0x0"],
"MM1": ["0x4546474800000000", "0x0"],
"MM2": ["0x0", "0x0"],
"MM3": ["0x4142434445464748", "0x0"],
"MM4": ["0x4546474800000000", "0x0"],
"MM5": ["0x0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x0
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
mov rax, 0x20
mov [rdx + 8 * 4], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 5], rax
mov rax, 0x40
mov [rdx + 8 * 6], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 7], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 0]
movq mm3, [rdx + 8 * 0]
movq mm4, [rdx + 8 * 0]
movq mm5, [rdx + 8 * 0]
movq mm6, [rdx + 8 * 2]
movq mm7, [rdx + 8 * 4]
psllq mm0, mm6
psllq mm1, mm7
movq mm7, [rdx + 8 * 6]
psllq mm2, mm7
psllq mm3, [rdx + 8 * 2]
psllq mm4, [rdx + 8 * 4]
psllq mm5, [rdx + 8 * 6]
hlt
unittests/ASM/TwoByte/0F_F4.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x000000000003FFFC", "0x0"],
"MM1": ["0x000000000003FFFC", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x414243440000FFFF
mov [rdx + 8 * 0], rax
mov rax, 0x5152535400007FFF
mov [rdx + 8 * 1], rax
mov rax, 0x6162636400000004
mov [rdx + 8 * 2], rax
mov rax, 0x7172737400000002
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
pmuludq mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
pmuludq mm1, mm2
hlt
unittests/ASM/TwoByte/0F_F5.asm
+35
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@@ -0,0 +1,35 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2A9FE7742F697C44", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
mov rax, 0x0
mov [rdx + 8 * 4], rax
mov [rdx + 8 * 5], rax
mov eax, dword [rdx + 8 * 0]
mov rbx, qword [rdx + 8 * 1]
movq mm0, [rdx + 8 * 0]
pmaddwd mm0, [rdx + 8 * 1]
hlt
unittests/ASM/TwoByte/0F_F8.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2020202020202020", "0x0"],
"MM1": ["0x2020202020202020", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x6162636465666768
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
psubb mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
psubb mm1, mm2
hlt
unittests/ASM/TwoByte/0F_F9.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2020202020202020", "0x0"],
"MM1": ["0x2020202020202020", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x6162636465666768
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
psubw mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
psubw mm1, mm2
hlt
unittests/ASM/TwoByte/0F_FA.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2020202020202020", "0x0"],
"MM1": ["0x2020202020202020", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x6162636465666768
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
psubd mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
psubd mm1, mm2
hlt
unittests/ASM/TwoByte/0F_FB.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0x2020202020202020", "0x0"],
"MM1": ["0x2020202020202020", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x6162636465666768
mov [rdx + 8 * 0], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 1], rax
mov rax, 0x4142434445464748
mov [rdx + 8 * 2], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 3], rax
movq mm0, [rdx]
psubq mm0, [rdx + 8 * 2]
movq mm1, [rdx]
movq mm2, [rdx + 8 * 2]
psubq mm1, mm2
hlt
unittests/ASM/TwoByte/0F_FC.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xA2A4A6A8AAACAEB0", "0x0"],
"MM1": ["0xA2A4A6A8AAACAEB0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddb mm0, mm2
paddb mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_FD.asm
+32
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@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xA2A4A6A8AAACAEB0", "0x0"],
"MM1": ["0xA2A4A6A8AAACAEB0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddw mm0, mm2
paddw mm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_FE.asm
+32
View File
@@ -0,0 +1,32 @@
%ifdef CONFIG
{
"RegData": {
"MM0": ["0xA2A4A6A8AAACAEB0", "0x0"],
"MM1": ["0xA2A4A6A8AAACAEB0", "0x0"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x4142434445464748
mov [rdx + 8 * 0], rax
mov rax, 0x5152535455565758
mov [rdx + 8 * 1], rax
mov rax, 0x6162636465666768
mov [rdx + 8 * 2], rax
mov rax, 0x7172737475767778
mov [rdx + 8 * 3], rax
movq mm0, [rdx + 8 * 0]
movq mm1, [rdx + 8 * 0]
movq mm2, [rdx + 8 * 2]
paddd mm0, mm2
paddd mm1, [rdx + 8 * 2]
hlt