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Merge pull request #157 from Sonicadvance1/rcp

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Implements support for rcpps/rcpss
This commit is contained in:
Ryan Houdek authored and GitHub committed 2020-04-29 16:03:38 -07:00
2 parents 056d017ac8 bf5dbdf143
commit 8f2f046fc8
4 files changed
+70 -2
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External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp
Vendored
+7 -2
View File
@@ -2847,7 +2847,9 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
// Scalar
switch (Op->Header.ElementSize) {
case 4: {
vrcpss(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[0].ID()));
mov(eax, 0x3f800000); // 1.0f
vmovd(xmm15, eax);
vdivss(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
break;
}
default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
@@ -2857,7 +2859,10 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
// Vector
switch (Op->Header.ElementSize) {
case 4: {
vrcpps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
mov(eax, 0x3f800000); // 1.0f
vmovd(xmm15, eax);
pshufd(xmm15, xmm15, 0);
vdivps(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
break;
}
default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+2
View File
@@ -5630,6 +5630,7 @@ void InstallOpcodeHandlers() {
{0x50, 1, &OpDispatchBuilder::MOVMSKOp<4>},
{0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 4, false>},
{0x52, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRSQRT, 4, false>},
{0x53, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRECP, 4, false>},
{0x54, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VAND, 16>},
{0x55, 1, &OpDispatchBuilder::ANDNOp},
{0x56, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
@@ -5826,6 +5827,7 @@ void InstallOpcodeHandlers() {
{0x2D, 1, &OpDispatchBuilder::CVTFPR_To_GPR<4, true>},
{0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 4, true>},
{0x52, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRSQRT, 4, true>},
{0x53, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFRECP, 4, true>},
{0x58, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFADD, 4>},
{0x59, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMUL, 4>},
{0x5A, 1, &OpDispatchBuilder::Scalar_CVT_Float_To_Float<8, 4>},
unittests/ASM/REP/F3_53.asm
+31
View File
@@ -0,0 +1,31 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x3f8000003f800000", "0x3f8000003f800000"],
"XMM1": ["0x408000003e800000", "0x4080000040800000"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x3f8000003f800000 ; 1.0
mov [rdx + 8 * 0], rax
mov rax, 0x3f8000003f800000
mov [rdx + 8 * 1], rax
mov rax, 0x4080000040800000 ; 4.0
mov [rdx + 8 * 2], rax
mov rax, 0x4080000040800000
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx + 8 * 0]
movapd xmm1, [rdx + 8 * 2]
rcpss xmm0, xmm0
rcpss xmm1, [rdx + 8 * 2]
hlt
unittests/ASM/TwoByte/0F_53.asm
+30
View File
@@ -0,0 +1,30 @@
%ifdef CONFIG
{
"RegData": {
"XMM0": ["0x3f8000003f800000", "0x3f8000003f800000"],
"XMM1": ["0x3e8000003e800000", "0x3e8000003e800000"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
mov rdx, 0xe0000000
mov rax, 0x3f8000003f800000 ; 1.0
mov [rdx + 8 * 0], rax
mov rax, 0x3f8000003f800000
mov [rdx + 8 * 1], rax
mov rax, 0x4080000040800000 ; 4.0
mov [rdx + 8 * 2], rax
mov rax, 0x4080000040800000
mov [rdx + 8 * 3], rax
movapd xmm0, [rdx + 8 * 0]
rcpps xmm0, xmm0
rcpps xmm1, [rdx + 8 * 2]
hlt