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JIT: make almost all the DEF_OPs common

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this deduplicates a bunch of #defines, letting us change the signature easier.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2025-05-19 13:42:59 -04:00
1 parent 30f3b545af
commit afce108ed7
10 files changed
+2 -21
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FEXCore/Source/Interface/Core/JIT/ALUOps.cpp
-4
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@@ -16,8 +16,6 @@ namespace FEXCore::CPU {
#define GRD(Node) (IROp->Size <= 4 ? GetDst<RA_32>(Node) : GetDst<RA_64>(Node))
#define GRS(Node) (IROp->Size <= 4 ? GetReg<RA_32>(Node) : GetReg<RA_64>(Node))
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
#define DEF_BINOP_WITH_CONSTANT(FEXOp, VarOp, ConstOp) \
DEF_OP(FEXOp) { \
auto Op = IROp->C<IR::IROp_##FEXOp>(); \
@@ -1651,6 +1649,4 @@ DEF_OP(FCmp) {
fcmp(EmitSubSize, Scalar1, Scalar2);
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp
-2
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@@ -10,7 +10,6 @@ $end_info$
#include "Interface/Core/JIT/JITClass.h"
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(CASPair) {
auto Op = IROp->C<IR::IROp_CASPair>();
LOGMAN_THROW_A_FMT(IROp->ElementSize == IR::OpSize::i32Bit || IROp->ElementSize == IR::OpSize::i64Bit, "Wrong element size");
@@ -473,5 +472,4 @@ DEF_OP(TelemetrySetValue) {
#endif
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
-2
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@@ -18,7 +18,6 @@ $end_info$
#include <FEXCore/Utils/MathUtils.h>
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(CallbackReturn) {
// spill back to CTX
@@ -483,5 +482,4 @@ DEF_OP(XGetBV) {
ubfx(ARMEmitter::Size::i64Bit, GetReg(Op->OutEDX), TMP1, 32, 32);
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/ConversionOps.cpp
-2
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@@ -9,7 +9,6 @@ $end_info$
#include "Interface/Context/Context.h"
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(VInsGPR) {
const auto Op = IROp->C<IR::IROp_VInsGPR>();
const auto OpSize = IROp->Size;
@@ -583,5 +582,4 @@ DEF_OP(Vector_F64ToI32) {
}
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/EncryptionOps.cpp
-2
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@@ -8,7 +8,6 @@ $end_info$
#include "Interface/Core/JIT/JITClass.h"
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(VAESImc) {
auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -346,5 +345,4 @@ DEF_OP(PCLMUL) {
}
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/JITClass.h
+2
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@@ -383,6 +383,8 @@ private:
#undef DEF_OP
};
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
[[nodiscard]]
fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread);
FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp
-2
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@@ -15,7 +15,6 @@ $end_info$
#include <FEXCore/Utils/MathUtils.h>
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(LoadContext) {
const auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -2587,5 +2586,4 @@ DEF_OP(VLoadNonTemporal) {
}
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/MiscOps.cpp
-2
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@@ -16,7 +16,6 @@ $end_info$
#include <FEXCore/Core/SignalDelegator.h>
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(AllocateGPR) {}
DEF_OP(AllocateGPRAfter) {}
@@ -271,5 +270,4 @@ DEF_OP(Yield) {
yield();
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/MoveOps.cpp
-2
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@@ -8,7 +8,6 @@ $end_info$
#include "Interface/Core/JIT/JITClass.h"
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
DEF_OP(Copy) {
auto Op = IROp->C<IR::IROp_Copy>();
@@ -39,5 +38,4 @@ DEF_OP(Swap2) {
// Implemented above
}
#undef DEF_OP
} // namespace FEXCore::CPU
FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
-3
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@@ -11,7 +11,6 @@ $end_info$
#include <FEXCore/Utils/MathUtils.h>
namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
#define DEF_UNOP(FEXOp, ARMOp, ScalarCase) \
DEF_OP(FEXOp) { \
@@ -4586,6 +4585,4 @@ DEF_OP(VFCopySign) {
}
}
#undef DEF_OP
} // namespace FEXCore::CPU