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JIT/AtomicOps: factor out elementsize
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed
1 parent
2d3d49b900
commit
bb064c7334
2 files changed
+45
-142
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@@ -69,8 +69,8 @@ DEF_OP(CASPair) {
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DEF_OP(CAS) {
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auto Op = IROp->C<IR::IROp_CAS>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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// DataSrc = *Src1
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// if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
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// This will write to memory! Careful!
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@@ -79,13 +79,6 @@ DEF_OP(CAS) {
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auto Desired = GetReg(Op->Desired.ID());
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auto MemSrc = GetReg(Op->Addr.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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mov(EmitSize, TMP2, Expected);
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casal(SubEmitSize, TMP2, Desired, MemSrc);
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@@ -96,9 +89,9 @@ DEF_OP(CAS) {
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ARMEmitter::SingleUseForwardLabel LoopExpected;
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Bind(&LoopTop);
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ldaxr(SubEmitSize, TMP2, MemSrc);
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if (OpSize == 1) {
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if (IROp->Size == 1) {
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cmp(EmitSize, TMP2, Expected, ARMEmitter::ExtendedType::UXTB, 0);
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} else if (OpSize == 2) {
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} else if (IROp->Size == 2) {
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cmp(EmitSize, TMP2, Expected, ARMEmitter::ExtendedType::UXTH, 0);
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} else {
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cmp(EmitSize, TMP2, Expected);
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@@ -120,19 +113,12 @@ DEF_OP(CAS) {
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DEF_OP(AtomicAdd) {
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auto Op = IROp->C<IR::IROp_AtomicAdd>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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staddl(SubEmitSize, Src, MemSrc);
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} else {
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@@ -147,19 +133,12 @@ DEF_OP(AtomicAdd) {
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DEF_OP(AtomicSub) {
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auto Op = IROp->C<IR::IROp_AtomicSub>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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neg(EmitSize, TMP2, Src);
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staddl(SubEmitSize, TMP2, MemSrc);
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@@ -175,19 +154,12 @@ DEF_OP(AtomicSub) {
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DEF_OP(AtomicAnd) {
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auto Op = IROp->C<IR::IROp_AtomicAnd>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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mvn(EmitSize, TMP2, Src);
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stclrl(SubEmitSize, TMP2, MemSrc);
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@@ -203,19 +175,12 @@ DEF_OP(AtomicAnd) {
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DEF_OP(AtomicCLR) {
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auto Op = IROp->C<IR::IROp_AtomicCLR>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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stclrl(SubEmitSize, Src, MemSrc);
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} else {
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@@ -230,19 +195,12 @@ DEF_OP(AtomicCLR) {
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DEF_OP(AtomicOr) {
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auto Op = IROp->C<IR::IROp_AtomicOr>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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stsetl(SubEmitSize, Src, MemSrc);
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} else {
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@@ -257,19 +215,12 @@ DEF_OP(AtomicOr) {
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DEF_OP(AtomicXor) {
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auto Op = IROp->C<IR::IROp_AtomicXor>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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steorl(SubEmitSize, Src, MemSrc);
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} else {
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@@ -284,18 +235,11 @@ DEF_OP(AtomicXor) {
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DEF_OP(AtomicNeg) {
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auto Op = IROp->C<IR::IROp_AtomicNeg>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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ARMEmitter::BackwardLabel LoopTop;
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Bind(&LoopTop);
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ldaxr(SubEmitSize, TMP2, MemSrc);
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@@ -333,19 +277,12 @@ DEF_OP(AtomicSwap) {
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DEF_OP(AtomicFetchAdd) {
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auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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ldaddal(SubEmitSize, Src, GetReg(Node), MemSrc);
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} else {
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@@ -361,19 +298,12 @@ DEF_OP(AtomicFetchAdd) {
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DEF_OP(AtomicFetchSub) {
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auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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neg(EmitSize, TMP2, Src);
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ldaddal(SubEmitSize, TMP2, GetReg(Node), MemSrc);
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@@ -390,19 +320,12 @@ DEF_OP(AtomicFetchSub) {
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DEF_OP(AtomicFetchAnd) {
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auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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mvn(EmitSize, TMP2, Src);
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ldclral(SubEmitSize, TMP2, GetReg(Node), MemSrc);
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@@ -419,19 +342,12 @@ DEF_OP(AtomicFetchAnd) {
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DEF_OP(AtomicFetchCLR) {
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auto Op = IROp->C<IR::IROp_AtomicFetchCLR>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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ldclral(SubEmitSize, Src, GetReg(Node), MemSrc);
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} else {
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@@ -447,19 +363,12 @@ DEF_OP(AtomicFetchCLR) {
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DEF_OP(AtomicFetchOr) {
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auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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ldsetal(SubEmitSize, Src, GetReg(Node), MemSrc);
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} else {
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@@ -475,19 +384,12 @@ DEF_OP(AtomicFetchOr) {
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DEF_OP(AtomicFetchXor) {
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auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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auto Src = GetReg(Op->Value.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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if (CTX->HostFeatures.SupportsAtomics) {
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ldeoral(SubEmitSize, Src, GetReg(Node), MemSrc);
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} else {
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@@ -503,18 +405,11 @@ DEF_OP(AtomicFetchXor) {
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DEF_OP(AtomicFetchNeg) {
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auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
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uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
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auto MemSrc = GetReg(Op->Addr.ID());
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const auto EmitSize = ConvertSize(IROp);
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const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
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OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
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OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ARMEmitter::SubRegSize::i8Bit;
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ARMEmitter::BackwardLabel LoopTop;
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Bind(&LoopTop);
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ldaxr(SubEmitSize, TMP2, MemSrc);
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@@ -166,9 +166,7 @@ private:
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}
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[[nodiscard]]
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ARMEmitter::SubRegSize ConvertSubRegSize16(const IR::IROp_Header* Op) {
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const auto ElementSize = Op->ElementSize;
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ARMEmitter::SubRegSize ConvertSubRegSize16(uint8_t ElementSize) {
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LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8 || ElementSize == 16, "Invalid size");
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return ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
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ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
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@@ -177,10 +175,20 @@ private:
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ARMEmitter::SubRegSize::i128Bit;
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}
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[[nodiscard]]
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ARMEmitter::SubRegSize ConvertSubRegSize16(const IR::IROp_Header* Op) {
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return ConvertSubRegSize16(Op->ElementSize);
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}
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[[nodiscard]]
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ARMEmitter::SubRegSize ConvertSubRegSize8(uint8_t ElementSize) {
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LOGMAN_THROW_AA_FMT(ElementSize != 16, "Invalid size");
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return ConvertSubRegSize16(ElementSize);
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}
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[[nodiscard]]
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ARMEmitter::SubRegSize ConvertSubRegSize8(const IR::IROp_Header* Op) {
|
||||
LOGMAN_THROW_AA_FMT(Op->ElementSize != 16, "Invalid size");
|
||||
return ConvertSubRegSize16(Op);
|
||||
return ConvertSubRegSize8(Op->ElementSize);
|
||||
}
|
||||
|
||||
[[nodiscard]]
|
||||
|
||||
Reference in new issue
Block a user