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Merge pull request #457 from Sonicadvance1/cpu_family
Changes CPU family reported by CPUID
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Stefanos Kornilios Mitsis Poiitidis authored and GitHub committed
commit
bd476bb8ea
2 files changed
+37
-89
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+31
-87
@@ -31,7 +31,7 @@ CPUIDEmu::FunctionResults CPUIDEmu::Function_01h() {
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Res.eax = 0 | // Stepping
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(0 << 4) | // Model
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(0 << 8) | // Family ID
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(0xF << 8) | // Family ID
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(0 << 12) | // Processor type
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(0 << 16) | // Extended model ID
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(0 << 20); // Extended family ID
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@@ -69,9 +69,9 @@ CPUIDEmu::FunctionResults CPUIDEmu::Function_01h() {
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(0 << 26) | // XSAVE
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(0 << 27) | // OSXSAVE
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(0 << 28) | // AVX
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(0 << 29) | // RDRAND
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(0 << 29) | // F16C
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(0 << 30) | // RDRAND
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(0 << 31); // Always returns zero
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(0 << 31); // Hypervisor always returns zero
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Res.edx =
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(1 << 0) | // FPU
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@@ -100,7 +100,7 @@ CPUIDEmu::FunctionResults CPUIDEmu::Function_01h() {
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(1 << 23) | // MMX
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(1 << 24) | // FXSAVE/FXRSTOR
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(1 << 25) | // SSE
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(1 << 26) | // SSE
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(1 << 26) | // SSE2
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(1 << 27) | // Self Snoop
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(1 << 28) | // Max APIC IDs reserved field is valid
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(1 << 29) | // Thermal monitor
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@@ -355,53 +355,26 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
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CTX = ctx;
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RegisterFunction(0, std::bind(&CPUIDEmu::Function_0h, this));
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RegisterFunction(1, std::bind(&CPUIDEmu::Function_01h, this));
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// Cache and TLB information
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RegisterFunction(2, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Serial Number(previously), now reserved
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RegisterFunction(3, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Deterministic cache parameters for each level
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RegisterFunction(4, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Monitor/mwait
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RegisterFunction(5, std::bind(&CPUIDEmu::Function_Reserved, this));
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// 2: Cache and TLB information
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// 3: Serial Number(previously), now reserved
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// 4: Deterministic cache parameters for each level
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// 5: Monitor/mwait
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// Thermal and power management
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RegisterFunction(6, std::bind(&CPUIDEmu::Function_06h, this));
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// Extended feature flags
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RegisterFunction(7, std::bind(&CPUIDEmu::Function_07h, this));
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// Reserved
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RegisterFunction(8, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Direct Cache Access information
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RegisterFunction(9, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Architectural performance monitoring
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RegisterFunction(0x0A, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Extended topology enumeration
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RegisterFunction(0x0B, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Reserved
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RegisterFunction(0x0C, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Processor extended state enumeration
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RegisterFunction(0x0D, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Reserved
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RegisterFunction(0x0E, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Intel RDT monitoring
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RegisterFunction(0x0F, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Intel RDT allocation enumeration
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RegisterFunction(0x10, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Reserved
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RegisterFunction(0x11, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Intel SGX capability enumeration
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RegisterFunction(0x12, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Reserved
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RegisterFunction(0x13, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Intel Processor trace
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RegisterFunction(0x14, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Timestamp counter information
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RegisterFunction(0x15, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Processor frequency information
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RegisterFunction(0x16, std::bind(&CPUIDEmu::Function_Reserved, this));
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// SoC vendor attribute enumeration
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RegisterFunction(0x17, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Hypervisor vendor string
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RegisterFunction(0x4000'0000, std::bind(&CPUIDEmu::Function_Reserved, this));
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// 9: Direct Cache Access information
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// 0x0A: Architectural performance monitoring
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// 0x0B: Extended topology enumeration
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// 0x0D: Processor extended state enumeration
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// 0x0F: Intel RDT monitoring
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// 0x10: Intel RDT allocation enumeration
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// 0x12: Intel SGX capability enumeration
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// 0x13: Reserved
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// 0x14: Intel Processor trace
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// 0x15: Timestamp counter information
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// 0x16: Processor frequency information
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// 0x17: SoC vendor attribute enumeration
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// Largest extended function number
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RegisterFunction(0x8000'0000, std::bind(&CPUIDEmu::Function_8000_0000h, this));
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@@ -413,48 +386,19 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
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RegisterFunction(0x8000'0003, std::bind(&CPUIDEmu::Function_8000_0003h, this));
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// Processor brand string continued
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RegisterFunction(0x8000'0004, std::bind(&CPUIDEmu::Function_8000_0004h, this));
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// L1 Cache and TLB identifiers
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RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_Reserved, this));
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// L2 Cache identifiers
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RegisterFunction(0x8000'0006, std::bind(&CPUIDEmu::Function_Reserved, this));
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// 0x8000'0005: L1 Cache and TLB identifiers
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// 0x8000'0006: L2 Cache identifiers
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// Advanced power management information
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RegisterFunction(0x8000'0007, std::bind(&CPUIDEmu::Function_8000_0007h, this));
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// Virtual and physical address sizes
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RegisterFunction(0x8000'0008, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Reserved
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RegisterFunction(0x8000'0009, std::bind(&CPUIDEmu::Function_Reserved, this));
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// SVM Revision
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RegisterFunction(0x8000'000A, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Reserved
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RegisterFunction(0x8000'000B, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'000C, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'000D, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'000E, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'000F, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0010, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0011, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0012, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0013, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0014, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0015, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0016, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0017, std::bind(&CPUIDEmu::Function_Reserved, this));
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RegisterFunction(0x8000'0018, std::bind(&CPUIDEmu::Function_Reserved, this));
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// TLB 1GB page identifiers
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RegisterFunction(0x8000'0019, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Performance optimization identifiers
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RegisterFunction(0x8000'001A, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Instruction based sampling identifiers
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RegisterFunction(0x8000'001B, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Lightweight profiling capabilities
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RegisterFunction(0x8000'001C, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Cache properties
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RegisterFunction(0x8000'001D, std::bind(&CPUIDEmu::Function_Reserved, this));
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// Extended APIC ID
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RegisterFunction(0x8000'001E, std::bind(&CPUIDEmu::Function_Reserved, this));
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// AMD Secure Encryption
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RegisterFunction(0x8000'001F, std::bind(&CPUIDEmu::Function_Reserved, this));
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// 0x8000'0008: Virtual and physical address sizes
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// 0x8000'000A: SVM Revision
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// 0x8000'0019: TLB 1GB page identifiers
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// 0x8000'001A: Performance optimization identifiers
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// 0x8000'001B: Instruction based sampling identifiers
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// 0x8000'001C: Lightweight profiling capabilities
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// 0x8000'001D: Cache properties
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// 0x8000'001E: Extended APIC ID
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// 0x8000'001F: AMD Secure Encryption
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}
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}
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+6
-2
@@ -27,8 +27,12 @@ public:
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};
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FunctionResults RunFunction(uint32_t Function) {
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LogMan::Throw::A(FunctionHandlers.find(Function) != FunctionHandlers.end(), "Don't have a CPUID handler for 0x%08x", Function);
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return FunctionHandlers[Function]();
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auto Handler = FunctionHandlers.find(Function);
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if (Handler == FunctionHandlers.end())
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return Function_Reserved();
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return Handler->second();
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}
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private:
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FEXCore::Context::Context *CTX;
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