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Merge pull request #2371 from lioncash/mul
ARMEmitter: Handle SVE predicated mul/div and finish off integer reduction category
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+97
-29
@@ -661,9 +661,45 @@ public:
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}
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// SVE integer multiply vectors (predicated)
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// XXX:
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void mul(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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constexpr uint32_t Op = 0b0000'0100'0001'0000'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b00, size, zd, pg, zn, zm);
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}
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void smulh(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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constexpr uint32_t Op = 0b0000'0100'0001'0000'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b10, size, zd, pg, zn, zm);
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}
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void umulh(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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constexpr uint32_t Op = 0b0000'0100'0001'0000'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b11, size, zd, pg, zn, zm);
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}
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// SVE integer divide vectors (predicated)
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// XXX:
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void sdiv(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_AA_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
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"Predicated divide only handles 32-bit or 64-bit elements");
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constexpr uint32_t Op = 0b0000'0100'0001'0100'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b00, size, zd, pg, zn, zm);
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}
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void udiv(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_AA_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
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"Predicated divide only handles 32-bit or 64-bit elements");
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constexpr uint32_t Op = 0b0000'0100'0001'0100'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b01, size, zd, pg, zn, zm);
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}
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void sdivr(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_AA_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
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"Predicated divide only handles 32-bit or 64-bit elements");
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constexpr uint32_t Op = 0b0000'0100'0001'0100'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b10, size, zd, pg, zn, zm);
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}
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void udivr(SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_AA_FMT(size == SubRegSize::i32Bit || size == SubRegSize::i64Bit,
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"Predicated divide only handles 32-bit or 64-bit elements");
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constexpr uint32_t Op = 0b0000'0100'0001'0100'0000'0000'0000'0000;
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SVEIntegerMulDivVectorsPredicated(Op, 0b11, size, zd, pg, zn, zm);
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}
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// SVE bitwise logical operations (predicated)
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void orr(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegisterMerge pg, FEXCore::ARMEmitter::ZRegister zdn, FEXCore::ARMEmitter::ZRegister zm) {
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LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size");
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@@ -692,27 +728,35 @@ public:
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// SVE Integer Reduction
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// SVE integer add reduction (predicated)
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// XXX:
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void saddv(SubRegSize size, DRegister vd, PRegister pg, ZRegister zn) {
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LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit,
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"saddv may only use 8-bit, 16-bit, or 32-bit elements.");
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constexpr uint32_t Op = 0b0000'0100'0000'0000'0010'0000'0000'0000;
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SVEIntegerReductionOperation(Op, 0b00, size, vd, pg, zn);
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}
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void uaddv(SubRegSize size, DRegister vd, PRegister pg, ZRegister zn) {
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LOGMAN_THROW_A_FMT(size == SubRegSize::i8Bit || size == SubRegSize::i16Bit || size == SubRegSize::i32Bit,
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"uaddv may only use 8-bit, 16-bit, or 32-bit elements.");
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constexpr uint32_t Op = 0b0000'0100'0000'0000'0010'0000'0000'0000;
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SVEIntegerReductionOperation(Op, 0b01, size, vd, pg, zn);
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}
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// SVE integer min/max reduction (predicated)
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void smaxv(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) {
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LOGMAN_THROW_A_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit || size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid subregsize size");
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void smaxv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
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SVEIntegerMinMaxReduction(Op, 0, 0, size, pg, zn, zd);
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SVEIntegerReductionOperation(Op, 0b00, size, vd, pg, zn);
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}
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void umaxv(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) {
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LOGMAN_THROW_A_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit || size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid subregsize size");
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void umaxv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
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SVEIntegerMinMaxReduction(Op, 0, 1, size, pg, zn, zd);
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SVEIntegerReductionOperation(Op, 0b01, size, vd, pg, zn);
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}
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void sminv(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) {
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LOGMAN_THROW_A_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit || size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid subregsize size");
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void sminv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
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SVEIntegerMinMaxReduction(Op, 1, 0, size, pg, zn, zd);
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SVEIntegerReductionOperation(Op, 0b10, size, vd, pg, zn);
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}
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void uminv(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) {
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LOGMAN_THROW_A_FMT(size == FEXCore::ARMEmitter::SubRegSize::i8Bit || size == FEXCore::ARMEmitter::SubRegSize::i16Bit || size == FEXCore::ARMEmitter::SubRegSize::i32Bit, "Invalid subregsize size");
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void uminv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0000'1000'001 << 13;
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SVEIntegerMinMaxReduction(Op, 1, 1, size, pg, zn, zd);
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SVEIntegerReductionOperation(Op, 0b11, size, vd, pg, zn);
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}
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// SVE constructive prefix (predicated)
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@@ -726,7 +770,18 @@ public:
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}
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// SVE bitwise logical reduction (predicated)
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// XXX
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void orv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
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SVEIntegerReductionOperation(Op, 0b00, size, vd, pg, zn);
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}
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void eorv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
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SVEIntegerReductionOperation(Op, 0b01, size, vd, pg, zn);
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}
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void andv(SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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constexpr uint32_t Op = 0b0000'0100'0001'1000'0010'0000'0000'0000;
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SVEIntegerReductionOperation(Op, 0b10, size, vd, pg, zn);
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}
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// SVE Bitwise Shift - Predicated
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// SVE bitwise shift by immediate (predicated)
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@@ -3809,19 +3864,6 @@ private:
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dc32(Instr);
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}
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// SVE integer min/max reduction (predicated)
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void SVEIntegerMinMaxReduction(uint32_t Op, uint32_t op, uint32_t U, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn, FEXCore::ARMEmitter::ZRegister zd) {
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uint32_t Instr = Op;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= op << 17;
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Instr |= U << 16;
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Instr |= pg.Idx() << 10;
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Instr |= Encode_rn(zn);
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Instr |= Encode_rd(zd);
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dc32(Instr);
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}
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// SVE constructive prefix (predicated)
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void SVEConstructivePrefixPredicated(uint32_t Op, uint32_t opc, uint32_t M, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn, FEXCore::ARMEmitter::ZRegister zd) {
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uint32_t Instr = Op;
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@@ -3987,6 +4029,32 @@ private:
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dc32(Instr);
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}
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void SVEIntegerMulDivVectorsPredicated(uint32_t op, uint32_t opc, SubRegSize size, ZRegister zd, PRegisterMerge pg, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_AA_FMT(zd.Idx() == zn.Idx(), "zd and zn must be the same register");
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LOGMAN_THROW_AA_FMT(pg <= PReg::p7, "Mul/Div operation can only use p0-p7 as a governing predicate");
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uint32_t Instr = op;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= opc << 16;
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Instr |= pg.Idx() << 10;
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Instr |= zm.Idx() << 5;
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Instr |= zd.Idx();
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dc32(Instr);
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}
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void SVEIntegerReductionOperation(uint32_t op, uint32_t opc, SubRegSize size, VRegister vd, PRegister pg, ZRegister zn) {
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LOGMAN_THROW_AA_FMT(size != SubRegSize::i128Bit, "Can't use 128-bit element size for reduction operation");
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LOGMAN_THROW_AA_FMT(pg <= PReg::p7, "Integer reduction operation can only use p0-p7 as a governing predicate");
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uint32_t Instr = op;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= opc << 16;
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Instr |= pg.Idx() << 10;
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Instr |= zn.Idx() << 5;
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Instr |= vd.Idx();
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dc32(Instr);
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}
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// SVE floating-point round to integral value
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void frintX(uint32_t opc, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) {
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// opc = round mode
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@@ -423,7 +423,7 @@ DEF_OP(VUMinV) {
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const auto Pred = OpSize == 16 ? PRED_TMP_16B
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: PRED_TMP_32B;
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uminv(SubRegSize, Dst.Z(), Pred, Vector.Z());
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uminv(SubRegSize, Dst, Pred, Vector.Z());
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} else {
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// Vector
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uminv(SubRegSize, Dst.Q(), Vector.Q());
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+82
-24
@@ -512,11 +512,54 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer min/max/difference
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer multiply vectors (predicated)") {
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// TODO: Implement in emitter.
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TEST_SINGLE(mul(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"mul z30.b, p7/m, z30.b, z29.b");
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TEST_SINGLE(mul(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"mul z30.h, p7/m, z30.h, z29.h");
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TEST_SINGLE(mul(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"mul z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(mul(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"mul z30.d, p7/m, z30.d, z29.d");
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TEST_SINGLE(smulh(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"smulh z30.b, p7/m, z30.b, z29.b");
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TEST_SINGLE(smulh(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"smulh z30.h, p7/m, z30.h, z29.h");
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TEST_SINGLE(smulh(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"smulh z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(smulh(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"smulh z30.d, p7/m, z30.d, z29.d");
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TEST_SINGLE(umulh(SubRegSize::i8Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"umulh z30.b, p7/m, z30.b, z29.b");
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TEST_SINGLE(umulh(SubRegSize::i16Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"umulh z30.h, p7/m, z30.h, z29.h");
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TEST_SINGLE(umulh(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"umulh z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(umulh(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"umulh z30.d, p7/m, z30.d, z29.d");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer divide vectors (predicated)") {
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// TODO: Implement in emitter.
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TEST_SINGLE(sdiv(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"sdiv z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(sdiv(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"sdiv z30.d, p7/m, z30.d, z29.d");
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TEST_SINGLE(udiv(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"udiv z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(udiv(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"udiv z30.d, p7/m, z30.d, z29.d");
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TEST_SINGLE(sdivr(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"sdivr z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(sdivr(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"sdivr z30.d, p7/m, z30.d, z29.d");
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TEST_SINGLE(udivr(SubRegSize::i32Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"udivr z30.s, p7/m, z30.s, z29.s");
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TEST_SINGLE(udivr(SubRegSize::i64Bit, ZReg::z30, PReg::p7.Merging(), ZReg::z30, ZReg::z29),
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"udivr z30.d, p7/m, z30.d, z29.d");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise logical operations (predicated)") {
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@@ -546,32 +589,34 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise logical operations
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer add reduction (predicated)") {
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// TODO: Implement in emitter.
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TEST_SINGLE(saddv(SubRegSize::i8Bit, DReg::d30, PReg::p7, ZReg::z29), "saddv d30, p7, z29.b");
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TEST_SINGLE(saddv(SubRegSize::i16Bit, DReg::d30, PReg::p7, ZReg::z29), "saddv d30, p7, z29.h");
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TEST_SINGLE(saddv(SubRegSize::i32Bit, DReg::d30, PReg::p7, ZReg::z29), "saddv d30, p7, z29.s");
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TEST_SINGLE(uaddv(SubRegSize::i8Bit, DReg::d30, PReg::p7, ZReg::z29), "uaddv d30, p7, z29.b");
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TEST_SINGLE(uaddv(SubRegSize::i16Bit, DReg::d30, PReg::p7, ZReg::z29), "uaddv d30, p7, z29.h");
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TEST_SINGLE(uaddv(SubRegSize::i32Bit, DReg::d30, PReg::p7, ZReg::z29), "uaddv d30, p7, z29.s");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer min/max reduction (predicated)") {
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TEST_SINGLE(smaxv(SubRegSize::i8Bit, ZReg::z30, PReg::p6, ZReg::z29), "smaxv b30, p6, z29.b");
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TEST_SINGLE(smaxv(SubRegSize::i16Bit, ZReg::z30, PReg::p6, ZReg::z29), "smaxv h30, p6, z29.h");
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TEST_SINGLE(smaxv(SubRegSize::i32Bit, ZReg::z30, PReg::p6, ZReg::z29), "smaxv s30, p6, z29.s");
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//TEST_SINGLE(smaxv(SubRegSize::i64Bit, ZReg::z30, PReg::p6, ZReg::z29), "smaxv d30, p6, z29.d");
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//TEST_SINGLE(smaxv(SubRegSize::i128Bit, ZReg::z30, PReg::p6, ZReg::z29), "smaxv q30, p6, z29.q");
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TEST_SINGLE(smaxv(SubRegSize::i8Bit, VReg::v30, PReg::p6, ZReg::z29), "smaxv b30, p6, z29.b");
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TEST_SINGLE(smaxv(SubRegSize::i16Bit, VReg::v30, PReg::p6, ZReg::z29), "smaxv h30, p6, z29.h");
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TEST_SINGLE(smaxv(SubRegSize::i32Bit, VReg::v30, PReg::p6, ZReg::z29), "smaxv s30, p6, z29.s");
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TEST_SINGLE(smaxv(SubRegSize::i64Bit, VReg::v30, PReg::p6, ZReg::z29), "smaxv d30, p6, z29.d");
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TEST_SINGLE(umaxv(SubRegSize::i8Bit, ZReg::z30, PReg::p6, ZReg::z29), "umaxv b30, p6, z29.b");
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TEST_SINGLE(umaxv(SubRegSize::i16Bit, ZReg::z30, PReg::p6, ZReg::z29), "umaxv h30, p6, z29.h");
|
||||
TEST_SINGLE(umaxv(SubRegSize::i32Bit, ZReg::z30, PReg::p6, ZReg::z29), "umaxv s30, p6, z29.s");
|
||||
//TEST_SINGLE(umaxv(SubRegSize::i64Bit, ZReg::z30, PReg::p6, ZReg::z29), "umaxv d30, p6, z29.d");
|
||||
//TEST_SINGLE(umaxv(SubRegSize::i128Bit, ZReg::z30, PReg::p6, ZReg::z29), "umaxv q30, p6, z29.q");
|
||||
TEST_SINGLE(umaxv(SubRegSize::i8Bit, VReg::v30, PReg::p6, ZReg::z29), "umaxv b30, p6, z29.b");
|
||||
TEST_SINGLE(umaxv(SubRegSize::i16Bit, VReg::v30, PReg::p6, ZReg::z29), "umaxv h30, p6, z29.h");
|
||||
TEST_SINGLE(umaxv(SubRegSize::i32Bit, VReg::v30, PReg::p6, ZReg::z29), "umaxv s30, p6, z29.s");
|
||||
TEST_SINGLE(umaxv(SubRegSize::i64Bit, VReg::v30, PReg::p6, ZReg::z29), "umaxv d30, p6, z29.d");
|
||||
|
||||
TEST_SINGLE(sminv(SubRegSize::i8Bit, ZReg::z30, PReg::p6, ZReg::z29), "sminv b30, p6, z29.b");
|
||||
TEST_SINGLE(sminv(SubRegSize::i16Bit, ZReg::z30, PReg::p6, ZReg::z29), "sminv h30, p6, z29.h");
|
||||
TEST_SINGLE(sminv(SubRegSize::i32Bit, ZReg::z30, PReg::p6, ZReg::z29), "sminv s30, p6, z29.s");
|
||||
//TEST_SINGLE(sminv(SubRegSize::i64Bit, ZReg::z30, PReg::p6, ZReg::z29), "sminv d30, p6, z29.d");
|
||||
//TEST_SINGLE(sminv(SubRegSize::i128Bit, ZReg::z30, PReg::p6, ZReg::z29), "sminv q30, p6, z29.q");
|
||||
TEST_SINGLE(sminv(SubRegSize::i8Bit, VReg::v30, PReg::p6, ZReg::z29), "sminv b30, p6, z29.b");
|
||||
TEST_SINGLE(sminv(SubRegSize::i16Bit, VReg::v30, PReg::p6, ZReg::z29), "sminv h30, p6, z29.h");
|
||||
TEST_SINGLE(sminv(SubRegSize::i32Bit, VReg::v30, PReg::p6, ZReg::z29), "sminv s30, p6, z29.s");
|
||||
TEST_SINGLE(sminv(SubRegSize::i64Bit, VReg::v30, PReg::p6, ZReg::z29), "sminv d30, p6, z29.d");
|
||||
|
||||
TEST_SINGLE(uminv(SubRegSize::i8Bit, ZReg::z30, PReg::p6, ZReg::z29), "uminv b30, p6, z29.b");
|
||||
TEST_SINGLE(uminv(SubRegSize::i16Bit, ZReg::z30, PReg::p6, ZReg::z29), "uminv h30, p6, z29.h");
|
||||
TEST_SINGLE(uminv(SubRegSize::i32Bit, ZReg::z30, PReg::p6, ZReg::z29), "uminv s30, p6, z29.s");
|
||||
//TEST_SINGLE(uminv(SubRegSize::i64Bit, ZReg::z30, PReg::p6, ZReg::z29), "uminv d30, p6, z29.d");
|
||||
//TEST_SINGLE(uminv(SubRegSize::i128Bit, ZReg::z30, PReg::p6, ZReg::z29), "uminv q30, p6, z29.q");
|
||||
TEST_SINGLE(uminv(SubRegSize::i8Bit, VReg::v30, PReg::p6, ZReg::z29), "uminv b30, p6, z29.b");
|
||||
TEST_SINGLE(uminv(SubRegSize::i16Bit, VReg::v30, PReg::p6, ZReg::z29), "uminv h30, p6, z29.h");
|
||||
TEST_SINGLE(uminv(SubRegSize::i32Bit, VReg::v30, PReg::p6, ZReg::z29), "uminv s30, p6, z29.s");
|
||||
TEST_SINGLE(uminv(SubRegSize::i64Bit, VReg::v30, PReg::p6, ZReg::z29), "uminv d30, p6, z29.d");
|
||||
}
|
||||
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE constructive prefix (predicated)") {
|
||||
TEST_SINGLE(movprfx(SubRegSize::i8Bit, ZReg::z30, PReg::p6.Merging(), ZReg::z29), "movprfx z30.b, p6/m, z29.b");
|
||||
@@ -586,7 +631,20 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE constructive prefix (predi
|
||||
//TEST_SINGLE(movprfx(SubRegSize::i128Bit, ZReg::z30, PReg::p6.Zeroing(), ZReg::z29), "movprfx z30.q, p6/z, z29.q");
|
||||
}
|
||||
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise logical reduction (predicated)") {
|
||||
// TODO: Implement in emitter.
|
||||
TEST_SINGLE(orv(SubRegSize::i8Bit, VReg::v30, PReg::p7, ZReg::z29), "orv b30, p7, z29.b");
|
||||
TEST_SINGLE(orv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "orv h30, p7, z29.h");
|
||||
TEST_SINGLE(orv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "orv s30, p7, z29.s");
|
||||
TEST_SINGLE(orv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "orv d30, p7, z29.d");
|
||||
|
||||
TEST_SINGLE(eorv(SubRegSize::i8Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv b30, p7, z29.b");
|
||||
TEST_SINGLE(eorv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv h30, p7, z29.h");
|
||||
TEST_SINGLE(eorv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv s30, p7, z29.s");
|
||||
TEST_SINGLE(eorv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "eorv d30, p7, z29.d");
|
||||
|
||||
TEST_SINGLE(andv(SubRegSize::i8Bit, VReg::v30, PReg::p7, ZReg::z29), "andv b30, p7, z29.b");
|
||||
TEST_SINGLE(andv(SubRegSize::i16Bit, VReg::v30, PReg::p7, ZReg::z29), "andv h30, p7, z29.h");
|
||||
TEST_SINGLE(andv(SubRegSize::i32Bit, VReg::v30, PReg::p7, ZReg::z29), "andv s30, p7, z29.s");
|
||||
TEST_SINGLE(andv(SubRegSize::i64Bit, VReg::v30, PReg::p7, ZReg::z29), "andv d30, p7, z29.d");
|
||||
}
|
||||
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE bitwise shift by immediate (predicated)") {
|
||||
TEST_SINGLE(asr(SubRegSize::i8Bit, ZReg::z30, PReg::p6.Merging(), ZReg::z30, 1), "asr z30.b, p6/m, z30.b, #1");
|
||||
|
||||
Reference in new issue
Block a user